Power Management Block for Use in a Non-Volatile Memory System

• US 20070106919A1
• Filed: 12/27/2006
• Published: 05/10/2007
• Est. Priority Date: 10/28/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chang, Robert, Qawami, Bahman, Sabet-Sharghi, Farshid, Yudin, Sergey
• Granted Patent: US 7,809,962 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 11/0763 by bit configuration check, e.g. of formats or tags
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G06F 11/1435 using file system or storage system metadata
• CPC Class Codes: G06F 11/1441 Resetting or repowering

Abstract

Methods and apparatus for enabling a power up process of a non-volatile memory to occur efficiently are disclosed. According to one aspect of the present invention, a method for utilizing a memory system that has a non-volatile memory with at least one reserved memory area includes providing power to the memory system, initializing the non-volatile memory, and writing a first signature into the reserved memory area. The first signature is arranged to indicate that the memory system was successfully initialized. In one embodiment, the method also includes executing a power down process on the memory system, and writing a second signature into the reserved memory area which indicates that the power down process has been executed.

Claims

1. A method for utilizing a memory system, the memory system including a non-volatile memory, the non-volatile memory including at least one reserved memory area, the method comprising:

providing power to the memory system;

initializing the non-volatile memory; and

writing a first signature into the at least one reserved memory area,

wherein the first signature is arranged to indicate that the memory system was successfully initialized.

2. The method of claim 1 further including:

executing a power down process on the memory system; and

writing a second signature into the at least one reserved memory area,

wherein the second signature is arranged to indicate that the power down process has been executed.

3. The method of claim 2 further including:

removing power from the memory system after writing the second signature into the at least one reserved memory area.

4. The method of claim 2 wherein writing the second signature into the at least one reserved memory area includes writing additional information with the second signature into the at least one reserved memory area.

5. The method of claim 2 wherein the at least one reserved memory area is a block, and writing the second signature into the at least one reserved memory area includes writing the second signature into a second page included in the block.

6. The method of claim 5 wherein writing the first signature into the at least one reserved memory area includes writing the first signature into a first page included in the block.

7. The method of claim 2 wherein executing the power down process includes at least one of completing a file copying process and resolving physical blocks associated with the non-volatile memory.

8. The method of claim 1 wherein writing the first signature into the at least one memory area includes writing additional information with the first signature into the at least one reserved memory area.

9. The method of claim 1 wherein the at least one reserved memory area is a block, and writing the first signature into the at least one reserved memory area includes writing the first signature into a first page included in the block.

10. The method of claim 1 wherein the non-volatile memory is a NAND flash memory.

11. A memory system comprising:

a non-volatile memory including at least one reserved memory area;

means for providing power;

means initializing the non-volatile memory; and

means for writing a first signature into the at least one reserved memory area,

wherein the first signature is arranged to indicate that the non-volatile memory was successfully initialized.

12. The memory system of claim 11 further including:

means for executing a power down process on the memory system; and

means for writing a second signature into the at least one reserved memory area,

wherein the second signature is arranged to indicate that the power down process has been executed.

13. The memory system of claim 12 wherein the at least one reserved memory area is a block, and writing the first signature into the at least one reserved memory area includes writing the first signature into a first page included in the block and writing the second signature into the at least one reserved memory area includes writing the second signature into a second page included in the block.

14. The memory system of claim 11 wherein the non-volatile memory is a NAND flash memory.

15. A memory device comprising:

code devices that are arranged to maintain at least one reserved memory area within a non-volatile memory;

code devices that cause a first signature to be written into the at least one reserved memory area to indicate that the non-volatile memory was successfully initialized when the non-volatile memory is successfully initialized; and

a memory section that is arranged to store the code devices.

16. The memory device of claim 15 further including:

code devices that cause a second signature to be written into the at least one reserved memory area to indicate that a power down process has been successfully executed when the power down process is successfully executed.

17. The memory device of claim 16 wherein the at least one reserved memory area is a block, and the code devices that cause the first signature to be written into the at least one reserved memory area include code devices that cause the first signature to be written into a first page included in the block and the code devices that cause the second signature to be written into the at least one reserved memory area include code devices that cause the second signature to be written into a second page included in the block.

18. The memory device of claim 15 wherein the code devices are one of software code devices and firmware code devices.

19-43. -43. (canceled)

44. A memory system comprising:

a non-volatile memory, the non-volatile memory including at least one reserved memory area;

a controller, the controller being arranged to initialize the non-volatile memory and to write a first signature into the at least one reserved memory area,

wherein the first signature is arranged to indicate that the memory system was successfully initialized.

45. The memory system of claim 44 wherein the controller is further arranged to execute a power down process on the memory system and to write a second signature into the at least one reserved memory area, wherein the second signature is arranged to indicate that the power down process has been executed.

46. The system of claim 44 wherein the non-volatile memory is a NAND flash memory.