Integrated circuit and method for testing memory on the integrated circuit

• US 20070106923A1
• Filed: 11/10/2005
• Published: 05/10/2007
• Est. Priority Date: 11/10/2005
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Waggoner, Gary, Aitken, Robert
• Granted Patent: US 8,145,958 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines

Abstract

An integrated circuit and method for testing memory on the integrated circuit are provided. The integrated circuit has processing logic for performing data processing operations on data, and a plurality of memory units for storing data for access by the processing logic. Further, memory test logic is provided to perform a sequence of tests in order to seek to detect memory defects in the memory units. The memory test logic comprises a plurality of test wrapper units, each test wrapper unit associated with one of the memory units and being operable to execute tests on the associated memory unit, and a test controller for controlling performance of the sequence of tests by communicating with each of the test wrapper units to provide test data defining each test to be executed by that test wrapper unit. Further, a first communication link is provided for connecting each of the test wrapper units directly to the test controller, and a second communication link is provided for connecting each test wrapper unit in an ordered sequence with the test controller. When controlling performance of the sequence of tests, the test controller provides first test data via the first communication link and second test data via the second communication link. It has been found that such an approach provides a particularly efficient and flexible technique for performing BIST functions within the integrated circuit.

Claims

1. An integrated circuit, comprising:

processing logic operable to perform data processing operations on data;

a plurality of memory units operable to store data for access by the processing logic; and

memory test logic operable to perform a sequence of tests in order to seek to detect memory defects in the plurality of memory units;

the memory test logic comprising;

a plurality of test wrapper units, each test wrapper unit associated with one of said memory units and being operable to execute tests on its associated memory unit;

a test controller operable to control performance of the sequence of tests by communicating with each of the test wrapper units to provide test data defining each test to be executed by that test wrapper unit;

a first communication link operable to connect each of the test wrapper units directly with the test controller; and

a second communication link operable to connect each test wrapper unit in an ordered sequence with the test controller;

when controlling performance of the sequence of tests, the test controller being operable to provide first test data via the first communication link and second test data via the second communication link.

2. An integrated circuit as claimed in claim 1, wherein the first test data is test data required by each of the test wrapper units, and the first communication link is used to broadcast that first test data to the plurality of test wrapper units.

3. An integrated circuit as claimed in claim 1, wherein the second test data is test wrapper unit specific test data, and the second communication link is used to output a sequence of blocks of second test data, each block being received by one of the test wrapper units.

4. An integrated circuit as claimed in claim 1, wherein the test controller is operable to periodically issue an identifier signal over the first communication link, the plurality of test wrapper units being operable to determine from the identifier signal whether test data provided subsequent to the identifier signal will be received over the first communication link or the second communication link.

5. An integrated circuit as claimed in claim 1, wherein test results obtained from execution of a test are communicated from each test wrapper unit to the test controller via the second communication link.

6. An integrated circuit as claimed in claim 1, wherein the first and second communication links are serial data links.

7. An integrated circuit as claimed in claim 1, wherein:

the test controller is operable to use a test clock signal and each of the plurality of test wrapper units are operable to use one or more system clock signals, each system clock signal having a higher frequency than the test clock signal; and

the test controller is operable to output a synchronisation signal over the first communication link to trigger the plurality of test wrapper units to read test data from the first or second communication links.

8. An integrated circuit as claimed in claim 1, wherein each test wrapper unit comprises:

a test engine operable to execute a test;

a plurality of registers operable to store test data for access by the test engine; and

register control logic operable to receive a register identifier over the first communication link, the register identifier identifying which of said plurality of registers is to receive test data subsequently received by the test wrapper unit from either the first communication link or the second communication link.

9. An integrated circuit as claimed in claim 8, wherein said plurality of registers include a command register, when the register identifier received over the first communication link identifies the command register, the subsequent data on the first communication link being stored in the command register to identify a command to be performed by the test engine.

10. An integrated circuit as claimed in claim 9, wherein said plurality of registers include an instruction register, when the command in the command register comprises a run test command, the test engine being operable to execute a test specified by an instruction in the instruction register.

11. An integrated circuit as claimed in claim 8, wherein:

said plurality of registers include a disable register, when the register identifier received over the first communication link identifies the disable register, the subsequent data received over the second communication link being stored in the disable register to identify whether the test wrapper unit is enabled or disabled; and

when the test wrapper unit is disabled the other registers in the plurality of registers are arranged to hold whatever data they held before the test wrapper unit was disabled.

12. An integrated circuit as claimed in claim 11, wherein:

said plurality of registers includes a shadow disable register, when the register identifier received over the first communication link identifies the disable register, the subsequent data received over the second communication link being shifted into the shadow disable register to update that shadow disable register; and

when the update of the shadow disable register is complete the content of the shadow disable register being copied to the disable register to identify whether the test wrapper unit is enabled or disabled.

13. An integrated circuit as claimed in claim 8, wherein:

each test wrapper unit has an input interface for receiving data from the second communication link and an output interface for outputting data on the second communication link, and is operable to selectively place registers of said plurality in a connecting path between said input interface and said output interface to allow data to be shifted in and out of those registers;

said plurality of registers include a bypass register, when the register identifier received over the first communication link identifies the bypass register, the subsequent data received over the second communication link being stored in the bypass register to identify whether the test wrapper unit is to be bypassed; and

when the bypass register indicates that the test wrapper unit is to be bypassed, the test wrapper unit being operable to logically connect the input interface to the output interface without placing any registers in the connecting path.

14. A method of performing a sequence of tests in order to seek to detect memory defects in a plurality of memory units within an integrated circuit, the integrated circuit including memory test logic comprising a plurality of test wrapper units and a test controller, each test wrapper unit being associated with one of said memory units, the method comprising the steps of:

employing each test wrapper unit to execute tests on its associated memory unit;

controlling performance of the sequence of tests by communicating via the test controller with each of the test wrapper units to provide test data defining each test to be executed by that test wrapper unit; and

when controlling performance of the sequence of tests, the test controller providing first test data via a first communication link connecting each of the test wrapper units directly with the test controller, and providing second test data via a second communication link connecting each test wrapper unit in an ordered sequence with the test controller.