Method of making nanowires

• US 20070108435A1
• Filed: 02/07/2006
• Published: 05/17/2007
• Est. Priority Date: 02/07/2005
• Status: Abandoned Application

• Current Assignee: David Salzman, Eric Harmon, Jerry Woodall
• Original Assignee: David Salzman, Eric Harmon, Jerry Woodall
• Inventors: Salzman, David, Woodall, Jerry, Harmon, Eric
• Application Number:
  US11/349,458
• Publication Number:
  US 20070108435A1
• Time in Patent Office: Days
• US Class Current: 257/9
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02392 Phosphides
• CPC Class Codes: H01L 21/02461 Phosphides
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/0259 Microstructure
• CPC Class Codes: H01L 21/02642 Mask materials other than SiO2 or SiN
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/7371 Vertical transistors

Abstract

A novel technique for manufacturing nanostructures and nanostructure is disclosed. The invention exploits techniques to deposit a second semiconductor material on a first semiconductor material with incomplete coverage of the second layer, and forming the nanostructures by filling the holes in the second semiconductor layer with a third semiconductor material. This allows the production of nanowires, nanorods, nanocylinders, and nanotubes with a controllable density and size distribution. Additionally, contact can be made to the bottom of the nanostructures through the first semiconductor layer allowing large area contacts to arrays of nanostructures to be formed. Similarly, contact can be made to the top of the nanostructure by direct deposition of a large area contacting layer. This allows the formation of nanostructure diodes and other nanostructure interconnections. Furthermore, a third large area contact to the second semiconductor layer can be used to modulate the conductivity of the arrays of nanostructures, enabling realization of a wide variety of nano transistors.

Claims

1. A means of forming a nanostructure entailing the steps of

(a) forming a second semiconductor material on top of a first semiconductor material under semiconductor growth conditions that provide incomplete coverage of said second material on the surface of the first semiconductor layer, said incomplete coverage including a multiplicity of holes in said second semiconductor material, and

(b) depositing a third semiconductor material that at least partially fills said holes to form a multiplicity of nanostructures.

2. The method of claim 1 wherein said first semiconductor material comprises a compound of Ga, Al, and/or In with N, As, P, and/or Sb.

3. The method of claim 1 wherein said second semiconductor material comprises a compound of Ga, Al, and/or In with N, As, P, and/or Sb.

4. The method of claim 1 wherein said third semiconductor material comprises a compound of Ga, Al, and/or In with N, As, P, and/or Sb.

5. The method of claim 1 wherein said first and third semiconductor materials each contain In and As.

6. The method of claim 1 wherein at least one of said first, second, or third semiconductor materials includes Si, Ge, and/or C.

7. The method of claim 1 where the density of holes is greater than 10⁶ cm⁻

2.

8. The method of claim 7 where the density of holes is greater than 10⁷ cm⁻

2.

9. The method of claim 8 where the density of holes is greater than 10⁸ cm⁻

2.

10. The method of claim 9 where the density of holes is greater than 10⁹ cm⁻

2.

11. A field-effect transistor whose drain is located in a first layer of a first semiconductor material, gate is located in a second layer of a second semiconductor material, source is located in a third layer of a third semiconductor material, and channel region comprises a plurality of nanostructures of said third semiconductor material embedded in said second semiconductor material.

12. The transistor of claim 11 further including a fourth layer of a fourth semiconductor material, and a source contact located in said fourth semiconductor material.

13. The transistor of claim 12 wherein said first and fourth semiconductor materials are n-type and said second semiconductor material is p-type.

14. The transistor of claim 12 wherein said first and fourth semiconductor materials are p-type and said second semiconductor material is n-type.

15. The transistor of claim 12 further including at least one further semiconductor material located between said third and said fourth semiconductor materials.

16. The transistor of claim 11 such that the concentrations of the elements comprising said first semiconductor material are each within 10% of the concentrations of the elements comprising said third semiconductor material.

17. A transistor defined in claims 11-15 except swapping the drain and source.

18. A bipolar junction transistor whose collector is located in a first semiconductor material, base contact is located in a second semiconductor material, emitter is located in a third semiconductor material, and active base region comprises a plurality of nanostructures of said third semiconductor material embedded in said second semiconductor material.

19. The transistor of claim 18 further including a fourth semiconductor material, and an emitter contact located in said fourth semiconductor material.

20. The transistor of claim 19 wherein said first and fourth semiconductor materials are n-type and said third semiconductor material is p-type.

21. The transistor of claim 19 wherein said first and fourth semiconductor materials are p-type and said third semiconductor material is n-type.

22. The transistor of claim 19 further including at least one further semiconductor material located between said third and said fourth semiconductor materials.

23. The transistor of claim 18 such that the concentrations of the elements comprising said first semiconductor material are each within 10% of the concentrations of the elements comprising said third semiconductor material.

24. A transistor defined in claims 18-23 except swapping the emitter and collector.

25. A unipolar junction transistor whose collector is located in a first semiconductor material, base contact is located in a second semiconductor material, emitter is located in a third semiconductor material, and active base region comprises a plurality of nanostructures of said third semiconductor material embedded in said second semiconductor material.

26. The transistor of claim 25 further including a fourth semiconductor material, and an emitter contact located in said fourth semiconductor material.

27. The transistor of claim 26 wherein said first, second, third and fourth semiconductor materials are each n-type or i-type.

28. The transistor of claim 26 wherein said first, second, third, and fourth semiconductor materials are each p-type or i-type.

29. The transistor of claim 26 further including at least one further semiconductor material located between said third and said fourth semiconductor materials.

30. The transistor of claim 26 such that the concentrations of the elements comprising said first semiconductor material are each within 10% of the concentrations of the elements comprising said third semiconductor material.

31. A transistor defined by claims 25-30 except swapping the emitter and collector.

32. A PN junction whose p-type region is located in a first semiconductor material and n-type region is located in a third semiconductor material embedded in a second semiconductor material, said n-type region penetrating into a plurality of holes in said second semiconductor material, said holes exposing said p-type region.