Trench mosfet

• US 20070108515A1
• Filed: 11/26/2004
• Published: 05/17/2007
• Est. Priority Date: 11/29/2003
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Hueting, Raymond, Hijzen, Erwin
• Granted Patent: US 7,696,599 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The invention relates to a trench MOSFET with drain (8), dπ ft region (10) body (12) and source (14). In order to improve the figure of meπt for use of the MOSFET as control and sync FETs, the trench (20) is partially filled with dielectric (24) adjacent to the drift region (10) and a graded doping profile is used in the dπft region (10)

Claims

1. An insulated gate field effect transistor, comprising:

a source region of first conductivity type;

a body region of second conductivity type opposite to the first conductivity type adjacent to the source region;

a drift region of exclusively the first conductivity type adjacent to the body region;

a drain region of first conductivity type adjacent to the drift region, so that body and drift regions are arranged between the source and drain regions, the drain region being of higher doping density than the drift region; and

insulated trenches extending from the source region through the body region and into the drift region, each trench having sidewalls, and including insulator on the sidewalls, and a conductive gate electrode between the insulating sidewall,

wherein the base of each trench is filled with an insulator plug adjacent to substantially all of the length of the drift region between the body region and drain region, and the respective gate electrode is provided in the trench over the plug adjacent to the source and body regions.

2. An insulated gate field effect transistor according to claim 1 wherein the doping concentration in the drift region is lower adjacent to the body region than adjacent to the drain region.

3. An insulated gate field effect transistor according to any preceding claim wherein the doping concentration in the body region is in the range of about 0.5×

10¹⁷ cm<sup>−

3</sup> to about 3×

10¹⁷ cm<sup>−

3</sup>, and the doping concentration in the drift region is in the range of about 1×

10¹⁵ cm<sup>−

3</sup> to about 2×

10¹⁷ cm<sup>−

3</sup>.

5. An insulated gate field effect transistor according to claim 1 having a semiconductor body having opposed first second major surfaces,

wherein the source region is at the first major surface over the region, the body region is over the drift region and the drift region is over the drain region, and

the trench extends from the first major surface towards the second major surface through the source, body and drift regions.

6. An insulated gate field effect transistor according to claim 5 having a plurality of cells, each cell having a source region at centre of the cell surrounded by the insulated trench.

7. An insulated gate field effect transistor according to claim 6 wherein the cells have a hexagonal geometry.

8. An insulated gate field effect transistor according to claim 6 wherein the trench has gate oxide on the sidewalls, and the of the trench adjacent to the drift region is filled with filler oxide between the gate oxide on the sidewalls on either side of the trench.

9. An insulated gate field effect transistor according to claim 5 having a plurality of cells, arranged as stripes across the first major surface with alternating trenches and source regions.

10. An insulated gate field effect transistor according to claim 6 wherein the cell pitch is in the range of about 0.2 microns to about 0.7 microns.

4. An insulated gate field effect transistor according to claim I wherein the plug is of dielectric filler filling the trench between the insulator on the sidewalls adjacent to the drain region.