Semiconductor device and fabrication method for the same

• US 20070108523A1
• Filed: 12/28/2006
• Published: 05/17/2007
• Est. Priority Date: 10/22/2003
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ogawa, Yasuyuki, Takafuji, Yutaka
• Granted Patent: US 7,436,027 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/26 Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01088 : Radium [Ra]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

In a semiconductor device including a monocrystalline thin film transistor 16a that has been formed on a monocrystalline Si wafer 100 and then is transferred to a insulating substrate 2, LOCOS oxidization is performed with respect to the element-isolation region of the monocrystalline Si wafer 100 so as to create a field oxide film (SiO₂ film) 104, and a marker 107 is formed on the field oxide film 104. With this structure, alignment of components may be performed based on a gate electrode 106 upon or after the transfer step.

Claims

1. A semiconductor device including a first device and a second device that are both provided on an insulating substrate wherein the first device is a transferred layer that has been transferred onto the insulating substrate at least with an active layer, a gate insulating film and a gate electrode that are previously formed thereon, and the second device is formed on the insulating substrate by being deposited thereon,

wherein:

the gate electrode is formed to be closer to the insulating substrate than the active layer, and the transferred layer includes (a) a marker whose position is detectable by light and (b) a light-transmissive insulating film formed on an opposite side to a side of the insulating substrate with respect to the marker.

2. The semiconductor device as set forth in claim 1, wherein:

the marker is formed on an element-isolation region in the transferred layer of the first device.

3. The semiconductor device as set forth in claim 2, wherein:

the element-isolation region is made up of light-transmissive insulating films locally provided, and the marker is formed on at least one of the light-transmissive insulating films.

4. The semiconductor device as set forth in claim 2, wherein:

the element-isolation region is made up of shallow trenches, each of which has a light-transmissive insulating film buried therein, and the marker is formed on the light-transmissive insulating film.

5. The semiconductor device as set forth in claim 1, wherein:

the light-transmissive insulating film is a SiO₂ film or a film mainly containing a SiO₂ film.

6. The semiconductor device as set forth in claim 1, wherein:

the marker is formed on a same layer of the first device as a layer having the gate electrode, from a same material as the gate electrode.

7. The semiconductor device as set forth in claim 1, wherein:

the transferred layer includes metal leads, and the marker is formed on a same layer of the first device as a layer having the metal leads, from a same material as the metal leads.

8. The semiconductor device as set forth in claim 1, wherein:

the first device is a monocrystalline Si thin film transistor.

9. A fabrication method of a semiconductor device including a first device and a second device that are both provided on an insulating substrate wherein the first device is a transferred substrate that has been transferred onto the insulating substrate at least with an active layer, a gate insulating film and a gate electrode that are previously formed thereon, and the second device is formed on the insulating substrate by being deposited thereon,

said method comprising the step of:

(a) bonding the transferred substrate with the insulating substrate;

(b) detaching a part of the transferred substrate after the step (a); and

(c) forming a marker detectable by light before the step (a) on the transferred substrate on a portion allowing detection by light, that is performed after the step (b) from an opposite side of the transferred substrate to a side facing the insulating substrate, the marker being used for alignment in semiconductor device forming steps that are performed after the step (a).

10. The fabrication method of a semiconductor device as set forth in claim 9, wherein:

in the step (c), the marker is formed on an element-isolation region of the first device.

11. The fabrication method of a semiconductor device as set forth in claim 10, further comprising the steps of:

(d) locally providing light-transmissive insulating films in the element-isolation region,

wherein;

in the step (c), the marker is formed on at least one of the light-transmissive insulating films.

12. The fabrication method of a semiconductor device as set forth in claim 10, further comprising the steps of:

(d) forming shallow trenches in the element-isolation region; and

(e) burying a light-transmissive insulating film in each of the shallow trenches,

wherein;

in the step (c), the marker is formed on the light-transmissive insulating film.

13. The fabrication method of a semiconductor device as set forth in claim 9, further comprising the step of:

(d) forming at least one interlayer insulating film made of a light-transmissive insulating film on a surface of the active layer after the active layer is exposed in a surface of a remaining part of the transferred substrate left on the insulating substrate.

14. The fabrication method of a semiconductor device as set forth in claim 13, further comprising the step of:

(e) forming a second marker on the interlayer insulating film in accordance with the marker, the second marker being used for alignment in semiconductor device forming steps that are performed after the step (e).

15. The fabrication method of a semiconductor device as set forth in claim 9, wherein:

the marker is used for alignment in the step (a).

16. The fabrication method of a semiconductor device as set forth in claim 15, further comprising the step of:

(d) forming a third marker on the insulating substrate, the third marker being used for alignment in the step (a) with the marker.

17. The fabrication method of a semiconductor device as set forth in claim 9, wherein:

the transferred substrate has a layer that is to be positioned after the step (a) on an opposite side of the insulating substrate with respect to the marker, the layer being formed from a SiO₂ film or a film mainly containing a SiO₂ film.

18. The fabrication method of a semiconductor device as set forth in claim 9, wherein:

the marker is formed on a layer having the gate electrode, from a same material as the gate electrode.

19. The fabrication method of a semiconductor device as set forth in claim 9, wherein:

the step (c) is performed before the step (a) by forming the marker and metal leads on the transferred substrate on a same layer from a same material.

20. The fabrication method of a semiconductor device as set forth in claim 9, further comprising the step of:

(d) implanting hydrogen ion, or hydrogen ion and a rare gas to the transferred substrate so as to form a hydrogen ion implanted region, before the step (a),

wherein;

in the step (b), a part of the transferred substrate is detached from the hydrogen ion implanted region through heat treatment.

21. The fabrication method of a semiconductor device as set forth in claim 9, wherein:

the first device is a monocrystalline Si thin film transistor.