NOVEL METHOD FOR FOUR DIRECTION LOW CAPACITANCE ESD PROTECTION

• US 20070108527A1
• Filed: 01/12/2007
• Published: 05/17/2007
• Est. Priority Date: 07/29/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Jian-Hsing, Chen, Shui
• Granted Patent: US 7,485,930 B2
• Time in Patent Office: Days
• US Class Current: 257/356
• CPC Class Codes: H01L 27/0255 using diodes as protective elements

Abstract

The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Claims

1. A low capacitance device structure with associated parasitic bipolar transistor on a substrate for the purpose of providing four-way electrostatic voltage discharge protection to the active semiconductor devices connected to the I/O logic circuit line and including ESD protection of the power bus system comprising:

isolation elements defining the active circuit area;

a first and second FET gate element upon said substrate surface;

a plurality of first, second and third doped regions of opposite dopent than said substrate;

a plurality of fourth and fifth doped regions within said substrate of similar dopent as said substrate;

an electrical connection system for said plurality of doped region;

a surface passivation layer for said ESD protection device.

2. The structure according to claim 1 wherein said substrate consists of silicon semiconductor material doped with an acceptor element such as oron to a concentration between 1E15 and 1E16 a/cm³.

3. The structure according to claim 1 wherein said isolation elements consist of field oxide elements or shallow trench isolation elements.

4. The structure according to claim 1 wherein said plurality of first, second and third doped regions are doped with a donor element such as As to a concentration between 1E20 and 1E21 a/cm³.

5. The structure according to claim 1 wherein said plurality of first doped regions form source and drain elements for said first gate element forming a first NFET device.

6. The structure according to claim 1 wherein said plurality of second doped regions form source and drain regions for said second gate element forming a second NFET device.

7. The structure according to claim 1 wherein said plurality of third doped regions form a N+ doped guard ring around said first NFET device.

8. The structure according to claim 1 wherein said plurality of fourth and fifth doped regions are doped with an acceptor element such as boron to a concentration between 1E20 and 1E21 a/cm³.

9. The structure according to claim 1 wherein said fourth doped region forms a P+ guard ring interposed between said first NFET device and said N+ guard ring and said fifth doped region forms a P+ guard ring around said second NFET device.

10. The structure according to claim 1 wherein said electrical connection system for said plurality of doped regions and said gate elements consists of aluminum metallurgy or aluminum doped with 1% silicon metallurgy.

11. The structure according to claim 1 wherein said first NFET source and gate and said second NFET source and gate and said P+ guard ring elements are connected by said electrical connector system to a second voltage source, typically ground.

12. The structure according to claim 1 wherein said NFET gate elements are comprised of an oxide insulator and a conductor element such as doped polysilicon.

13. The structure according to claim 1 wherein said first NFET drain is connected by said electrical connector system to said I/O logic circuit line.

14. The structure according to claim 1 wherein said second NFET drain and said N+ guard ring are connected by said electrical connector system to a first voltage source, Vcc.