High performance system-on-chip inductor using post passivation process

• US 20070108551A1
• Filed: 01/12/2007
• Published: 05/17/2007
• Est. Priority Date: 05/27/2003
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Application Number:
  US11/653,171
• Publication Number:
  US 20070108551A1
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A system and method for forming post passivation inductors, and related structures, is described. High quality electrical components, such as inductors and transformers, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. A circuit component comprising:

a silicon substrate;

a first polymer island over said silicon substrate; and

a first coil over said first polymer island, wherein each shortest distance between each point on the perimeter of said first polymer island and said first coil is smaller than the greatest traverse dimension of said first coil.

2. The circuit component of claim 1 further comprising a second polymer island over said silicon substrate and a second coil over said second polymer island, wherein said second polymer island is isolated from said first polymer island.

3. The circuit component of claim 1 further comprising a polymer layer over said first coil.

4. The circuit component of claim 1, wherein said first coil comprises a titanium-containing layer and a gold layer over said titanium-containing layer.

5. The circuit component of claim 1, wherein said first coil comprises a gold layer having a thickness of between 1 and 20 microns.

6. The circuit component of claim 1 further comprising a metallization structure over said silicon substrate and a passivation layer over said metallization structure, wherein said first polymer island is over said passivation layer.

7. The circuit component of claim 6, wherein said first coil is connected to said metallization structure through an opening in said first polymer island.

8. The circuit component of claim 6, wherein said first coil has a terminal for external connection, not connected to said metallization structure.

9. The circuit component of claim 6, wherein said passivation layer comprises nitride.

10. The circuit component of claim 6 further comprising a transistor in or on said silicon substrate.

11. The circuit component of claim 1, wherein said first polymer island comprises polyimide.

12. The circuit component of claim 1, wherein said first polymer island has a thickness of between 2 and 150 micrometers.

13. A circuit component comprising:

a silicon substrate;

a first polymer island over said silicon substrate, wherein said first polymer island has a perimeter with first and second sides opposite and substantially parallel to each other; and

a first coil over said first polymer island, wherein a shortest distance between a point on said first side and said first coil is smaller than the greatest traverse dimension of said first coil, and a shortest distance between a point on said second side and said first coil is smaller than the greatest traverse dimension of said first coil.

14. The circuit component of claim 13 further comprising a second coil over said first polymer island, wherein a shortest distance between a point on said first side and said second coil is smaller than the greatest traverse dimension of said second coil, and a shortest distance between a point on said second side and said second coil is smaller than the greatest traverse dimension of said second coil.

15. The circuit component of claim 13 further comprising a second polymer island over said silicon substrate and a second coil over said second polymer island, wherein said second polymer island is isolated from said first polymer island.

16. The circuit component of claim 13 further comprising a polymer layer over said first coil.

17. The circuit component of claim 13, wherein said first coil comprises a titanium-containing layer and a gold layer over said titanium-containing layer.

18. The circuit component of claim 13, wherein said first coil comprises a gold layer having a thickness of between 1 and 20 microns.

19. The circuit component of claim 13 further comprising a metallization structure over said silicon substrate and a passivation layer over said metallization structure, wherein said first polymer island is over said passivation layer.

20. The circuit component of claim 19, wherein said first coil is connected to said metallization structure through an opening in said first polymer island.

21. The circuit component of claim 19, wherein said first coil has a terminal for external connection, not connected to said metallization structure.

22. The circuit component of claim 19, wherein said passivation layer comprises nitride.

23. The circuit component of claim 19 further comprising a transistor in or on said silicon substrate.

24. The circuit component of claim 13, wherein said first polymer island comprises polyimide.

25. The circuit component of claim 13, wherein said first polymer island has a thickness of between 2 and 150 micrometers.

26. A circuit component comprising:

a silicon substrate;

a first polymer island over said silicon substrate; and

multiple first coils over said first polymer island, wherein said multiple first coils are all coils over said first polymer island, wherein each side of the perimeter of said first polymer island has a point with a shortest distance to one of said all coils over said first polymer island smaller than the greatest transverse dimension of said one of said all coils over said first polymer island.

27. The circuit component of claim 26 further comprising a second polymer island over said silicon substrate and a second coil over said second polymer island, wherein said second polymer island is isolated from said first polymer island.

28. The circuit component of claim 26 further comprising a polymer layer over said multiple first coils.

29. The circuit component of claim 26, wherein one of said multiple first coils comprises a titanium-containing layer and a gold layer over said titanium-containing layer.

30. The circuit component of claim 26, wherein one of said multiple first coils comprises a gold layer having a thickness of between 1 and 20 microns.

31. The circuit component of claim 26 further comprising a metallization structure over said silicon substrate and a passivation layer over said metallization structure, wherein said first polymer island is over said passivation layer.

32. The circuit component of claim 31, wherein one of said multiple first coils is connected to said metallization structure through an opening in said first polymer island.

33. The circuit component of claim 31, wherein one of said multiple first coils has a terminal for external connection, not connected to said metallization structure.

34. The circuit component of claim 31, wherein said passivation layer comprises nitride.

35. The circuit component of claim 31 further comprising a transistor in or on said silicon substrate.

36. The circuit component of claim 26, wherein said first polymer island comprises polyimide.

37. The circuit component of claim 26, wherein said first polymer island has a thickness of between 2 and 150 micrometers.

38. A die comprising:

a silicon substrate;

a first polymer island over said silicon substrate;

a second polymer island over said silicon substrate, wherein said first and second polymer islands are isolated from each other and are at a same horizontal level;

a first metal trace over said first polymer island; and

a second metal trace over said second polymer island.

39. The die of claim 38, wherein said first metal trace comprises a coil.

40. The die of claim 38, wherein said second metal trace comprises a coil.

41. The die of claim 38 further comprising a polymer layer over said first and second metal traces.

42. The die of claim 38, wherein said first metal trace comprises a titanium-containing layer and a gold layer over said titanium-containing layer.

43. The die of claim 38, wherein said first metal trace comprises a gold layer having a thickness of between 1 and 20 microns.

44. The die of claim 38 further comprising a metallization structure over said silicon substrate and a passivation layer over said metallization structure, wherein said first and second polymer islands are over said passivation layer.

45. The die of claim 44, wherein said first metal trace has a first terminal for external connection, not connected to said metallization structure.

46. The die of claim 44, wherein said first metal trace has a second terminal for external connection, not connected to said metallization structure.

47. The die of claim 44, wherein said first metal trace is connected to said metallization structure through an opening in said first polymer island.

48. The die of claim 44, wherein said passivation layer comprises nitride.

49. The die of claim 44 further comprising a transistor in or on said silicon substrate.

50. The die of claim 38, wherein said first polymer island comprises polyimide.

51. The die of claim 38, wherein said first polymer island has a thickness of between 2 and 150 micrometers.