Multilayer wiring board, manufacturing method thereof, semiconductor device, and wireless electronic device

• US 20070108588A1
• Filed: 01/16/2007
• Published: 05/17/2007
• Est. Priority Date: 07/18/2002
• Status: Active Grant

• Current Assignee: Etsuo Mizushima, Hiroyuki Kuriya, Kazuhisa Otsuka, Kazunori Yamamoto, Ken Madarame, Masanori Yamaguchi, Yasushi Shimada, Yoshitaka Hirata, Yuichi Shimayama, Yuusuke Kondou
• Original Assignee: Etsuo Mizushima, Hiroyuki Kuriya, Kazuhisa Otsuka, Kazunori Yamamoto, Ken Madarame, Masanori Yamaguchi, Yasushi Shimada, Yoshitaka Hirata, Yuichi Shimayama, Yuusuke Kondou
• Inventors: Shimada, Yasushi, Kuriya, Hiroyuki, Yamamoto, Kazunori, Hirata, Yoshitaka, Yamaguchi, Masanori, Otsuka, Kazuhisa, Shimayama, Yuichi, Kondou, Yuusuke, Mizushima, Etsuo, Madarame, Ken
• Granted Patent: US 7,592,250 B2
• Time in Patent Office: Days
• US Class Current: 257/691
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/0347 Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias reinforcing the conductive pattern H05K3/24
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A multilayer wiring board exhibiting excellent moldability and having a capacitor where variation of capacitance is suppressed, its producing method, a semiconductor device mounting a semiconductor chip on the multilayer wiring board, and a wireless electronic device mounting the semiconductor device.

Claims

1. A manufacturing method of a multilayer wiring board which includes a plurality of insulating layers, a plurality of conductive layers, a conductive non-through hole for electrically connecting the plurality of conductive layers to each other, and a capacitor produced by forming electrodes on upper and lower surfaces of at least one insulating layer containing a high-dielectric material, comprising at least:

the step of forming conductive patterns including one of the electrodes;

the step of filling and hardening an insulating material different from the high-dielectric material in a recessed portion between the conductive patterns;

the step of planarizing the surfaces of the conductive patterns and the surface of the insulating material filled and hardened in the recessed portion between the conductive patterns by polishing; and

the step of heating and laminating a metal foil having the high-dielectric material in a semi-hardened state.

2. The manufacturing method of a multilayer wiring board according to claim 1, further comprising a step of forming a conductive pattern including another of the electrodes by etching the metal foil.

7. The manufacturing method of a multilayer wiring board according to claim 1, further comprising the step of forming an inductor in at least one of the conductive layers.

9. A semiconductor device wherein a semiconductor chip is mounted on a multilayer wiring board manufactured by a manufacturing method according to claim 1.

10. A wireless electronic device wherein a semiconductor device according to claim 9 is mounted.

3. The manufacturing method of a multilayer wiring board which includes a plurality of insulating layers, a plurality of conductive layers, a conductive hole for electrically connecting the plurality of conductive layers to each other, and a capacitor comprising at least one of the insulating layers containing a high-dielectric material having a specific inductive capacity ranging from 20 to 100 at 25°

C. , 1 MHz and produced by forming electrodes on upper and lower surfaces of the insulating layer, wherein, in formation of a conductive pattern, the same substrate is exposed a plurality of times such that a pattern exposure area of a photosensitive resist is set at 1 to 250 cm²/time.

4. The manufacturing method of a multilayer wiring board according to claim 3, wherein, an electrode, of the electrodes, has a thickness ranging from 1 to 18 μ

m, and exposure is performed the plurality of times in formation of the conductive pattern including the electrode.

5. The manufacturing method of a multilayer wiring board according to claim 3, wherein a photomask consisting of an inorganic material is used in pattern exposure of the photosensitive resist.

6. The manufacturing method of a multilayer wiring board according to claim 3, wherein the conductive pattern including the electrode is formed by etching and removing an unnecessary portion of a conductive layer.

8. The manufacturing method of a multilayer wiring board according to claim 3, further comprising the step of forming an inductor in at least one of the conductive layers.

11. A semiconductor device wherein a semiconductor chip is mounted on a multilayer wiring board manufactured by a manufacturing method according to claim 3.

12. A wireless electronic device wherein a semiconductor device according to claim 11 is mounted.