FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROBE CARD

• US 20070108997A1
• Filed: 11/02/2006
• Published: 05/17/2007
• Est. Priority Date: 11/11/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Motoyama, Yasuhiro, Nakamura, Seigo, Horigome, Yoshimi, Natori, Iwao
• Granted Patent: US 7,688,086 B2
• Time in Patent Office: Days
• US Class Current: 324/754.30
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735

Abstract

To provide a technique of firmly bringing a stylus and a test pad into contact with each other in carrying out a probe testing summarizingly for plural chips by using a prober having the stylus formed by a technique of manufacturing a semiconductor integrated circuit device, plane patterns of respective wirings are formed such that a wiring and a wiring electrically connected to the wiring or a wiring which is not electrically connected to the wiring overlap each other, and a plane pattern arranged with both of the wiring and the wiring is constituted at upper portions of probes. Further, patterns of the wirings are formed such that an interval of arranging the wirings and a density of arranging the wirings become uniform at respective wiring layers in a thin film sheet.

Claims

1. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:

(a) preparing a semiconductor wafer partitioned into a plurality of chip regions, formed with semiconductor integrated circuits to each of the chip regions, and formed with a plurality of first electrodes electrically connected to the semiconductor integrated circuits on a main face thereof;

(b) preparing a first card including a first sheet formed with a first wiring substrate formed with a first wiring, a plurality of contact terminals for being brought into contact with the first electrodes, a plurality of second wirings electrically connected to the contact terminals and a plurality of third wirings which are not electrically connected to the contact terminals, wherein the second wirings are electrically connected to the first wirings and front ends of the contact terminals are held by the first wiring substrate opposedly to the main face of the semiconductor wafer, and a press mechanism for pressing a first region of the first sheet formed with the contact terminals from a back face side;

(c) carrying out an electric testing of the semiconductor integrated circuits by bringing the front ends of the contact terminals into contact with the first electrodes;

wherein the second wirings and the third wirings are formed by plural wiring layers in the first sheet; and

wherein the second wirings or the third wirings are arranged at positions in correspondence with respective upper portions of the contact terminals in the respective plural wiring layers.

2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a density of a plurality of wirings including the second wirings and the third wirings is made to be uniform in each of the plural wiring layers.

3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein widths and intervals of the wirings including the second wirings and the third wirings are made to be uniform in each of the plural the wiring layers.

4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the (c) step is carried out summarizingly for two of the chip regions arranged to be contiguous to each other in parallel in the semiconductor wafer.

5. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:

(a) preparing a semiconductor wafer partitioned into a plurality of chip regions, formed with semiconductor integrated circuits to each of the chip regions, and formed with a plurality of first electrodes electrically connected to the semiconductor integrated circuits on a main face thereof;

(b) preparing a first card including a first sheet formed with a first wiring substrate formed with a first wiring, a plurality of contact terminals for being brought into contact with the first electrodes, a plurality of second wirings electrically connected to the contact terminals and a plurality of third wirings which are not electrically connected to the contact terminals, wherein the second wirings are electrically connected to the first wirings and front ends of the contact terminals are held by the first wiring substrate opposedly to the main face of the semiconductor wafer, and a press mechanism for pressing a first region of the first sheet formed with the contact terminals from a back face side;

(c) carrying out an electric testing of the semiconductor integrated circuits by bringing the front ends of the contact terminals into contact with the first electrodes;

wherein the second wirings and the third wirings are formed by plural wiring layers in the first sheet; and

wherein only the second wirings included in the first wiring layer at a lowermost layer in the plural wiring layers are arranged at positions in correspondence with respective upper portions of the contact terminals in the first sheet.

6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein a density of a plurality of wirings including the second wirings and the third wirings is made to be uniform in each of the plural wiring layers.

7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein widths and intervals of the wirings including the second wirings and the third wirings are made to be uniform in each of the plural the wiring layers.

8. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the (c) step is carried out summarizingly for the chip regions diagonally contiguous to each other in the semiconductor wafer.

9. A method of manufacturing a semiconductor integrated circuit device comprising the steps of:

(a) preparing a semiconductor wafer partitioned into a plurality of chip regions, formed with semiconductor integrated circuits to each of the chip regions, and formed with a plurality of first electrodes electrically connected to the semiconductor integrated circuits on a main face thereof;

(b) preparing a first card including a first sheet formed with a first wiring substrate formed with a first wiring, a plurality of contact terminals for being brought into contact with the first electrodes, a plurality of second wirings electrically connected to the contact terminals and a plurality of third wirings which are not electrically connected to the contact terminals, wherein the second wirings are electrically connected to the first wirings and front ends of the contact terminals are held by the first wiring substrate opposedly to the main face of the semiconductor wafer, and a press mechanism for pressing a first region of the first sheet formed with the contact terminals from a back face side;

(c) carrying out an electric testing of the semiconductor integrated circuits by bringing the front ends of the contact terminals into contact with the first electrodes;

wherein the second wirings and the third wirings are formed by one wiring layer in the first sheet; and

wherein the (c) step is carried out summarizingly for two or more of the chip regions aligned to be remote from each other by one or more part of the chip regions in the semiconductor wafer.

10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein a density of a plurality of wirings including the second wirings and the third wirings is made to be uniform in the wiring layer.

11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein widths and intervals of the wirings including the second wirings and the third wirings are made to be uniform in the wiring layer.

12. A probe card comprising:

a first wiring substrate formed with a first wiring;

a first sheet formed with a plurality of contact terminals for being brought into contact with a plurality of first electrodes formed at a main face of a semiconductor wafer, a plurality of second wirings electrically connected to the contact terminals and a plurality of third wirings which are not electrically connected to the contact terminals, wherein the second wirings are electrically connected to the first wirings and front ends of the contact terminals are held by the first wiring substrate opposedly to the main face of the semiconductor wafer; and

a press mechanism for pressing a first region of the first sheet formed with the contact terminals from a back face side;

wherein the second wirings and the third wirings are formed by plural wiring layers in the first sheet; and

wherein the second wirings or the third wirings are arranged at positions in correspondence with respective upper portions of the contact terminals in each of the plural wiring layers.

13. The probe card according to claim 12, wherein a density of a plurality of wirings including the second wirings and the third wirings is made to be uniform in each of the plural wiring layers.

14. The probe card according to claim 13, wherein widths and intervals of the wirings including the second wirings and the third wirings are made to be uniform in each of the plural the wiring layers.

15. The probe card according to claim 12, wherein the first electrodes with which the contact terminals are brought into contact in one motion are formed in two chip regions selected in the semiconductor wafer;

and

wherein the two chip regions are aligned contiguously.

16. A probe card comprising:

a first wiring substrate formed with a first wiring;

a first sheet formed with a plurality of contact terminals for being brought into contact with a plurality of first electrodes formed at a main face of a semiconductor wafer, a plurality of second wirings electrically connected to the contact terminals and a plurality of third wirings which are not electrically connected to the contact terminals, wherein the second wirings are electrically connected to the first wirings and front ends of the contact terminals are held by the first wiring substrate opposedly to the main face of the semiconductor wafer; and

a press mechanism for pressing a first region of the first sheet formed with the contact terminals from a back face side;

wherein the second wirings and the third wirings are formed by plural wiring layers in the first sheet; and

wherein only the second wirings included in a first wiring layer of a lowermost layer in the plural wiring layers are arranged at positions in correspondence with respective upper portions of the contact terminals in the first sheet.

17. The probe card according to claim 16, wherein a density of a plurality of wirings including the second wirings and the third wirings is made to be uniform in each of the plural wiring layers.

18. The probe card according to claim 17, wherein widths and intervals of the wirings including the second wirings and the third wirings are made to be uniform in each of the plural wiring layers.

19. The probe card according to claim 16, wherein the first electrodes with which the contact terminals are brought into contact in one motion are formed in the chip regions selected in the semiconductor wafer;

and

wherein the chip regions are contiguous to each other diagonally.

20. A probe card comprising:

a first wiring substrate formed with a first wiring;

a first sheet formed with a plurality of contact terminals for being brought into contact with a plurality of first electrodes formed at a main face of a semiconductor wafer, a plurality of second wirings electrically connected to the contact terminals and a plurality of third wirings which are not electrically connected to the contact terminals, wherein the second wirings are electrically connected to the first wirings and front ends of the contact terminals are held by the first wiring substrate opposedly to the main face of the semiconductor wafer; and

a press mechanism for pressing a first region of the first sheet formed with the contact terminals from a back face side;

wherein the second wirings and the third wirings are formed by one wiring layer in the first sheet; and

wherein the first electrodes with which the contact terminals are brought into contact in one motion are formed in the chip regions selected in the semiconductor wafer and aligned to be remote from each other by one or more part of the chip regions.

21. The probe card according to claim 20, wherein a density of a plurality of wirings including the second wirings and the third wirings is made to be uniform in the wiring layer.

22. The probe card according to claim 21, wherein widths and intervals of the wirings including the second wirings and the third wirings are made to be uniform in the wiring layer.