Buffer management in vector graphics hardware

• US 20070109309A1
• Filed: 11/15/2005
• Published: 05/17/2007
• Est. Priority Date: 11/15/2005
• Status: Active Grant

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: Bitboys Oy (Advanced Micro Devices, Inc.)
• Inventors: Tuomi, Mika
• Granted Patent: US 8,294,731 B2
• Time in Patent Office: Days
• US Class Current: 345/568
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture

Abstract

A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.

Claims

1. A processor unit for processing vector graphics primitives, the processor unit comprising:

counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel;

a bus for receiving instructions and data;

a first internal buffer configured to store at least one indicator bit value for each pixel; and

determination logic configured to determine whether or not to retrieve and to retrieve the counter value from a memory based on the indicator bit values.

2. The processor unit of claim 1, further comprising:

a second internal buffer configured to store limited values for each counter,

wherein the determination logic is further configured to determine whether or not to retrieve the limited counter values from the second buffer.

3. The processor unit of claim 2, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has not changed.

4. The processor unit of claim 2, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has to be retrieved from an external memory.

5. The processor unit of claim 2, wherein the indicator bits of the first buffer include values for indicating a range of the second buffer from which the limited value of each counter is retrieved.

6. The processor unit of claim 1, wherein the memory is an external memory configured to store counter values for each pixel to be processed, and the bus is a bi-directional bus configured to retrieve counter values from the external memory.

7. The processor unit of claim 1, wherein the memory is an internal memory configured to store counter values for each pixel to be processed, and the bus is a unidirectional bus configured to receive instructions and data.

8. The processor unit of claim 1, wherein a memory is configured to store complete counter values for each sub-pixel having a counter.

9. The processor unit of claim 1, wherein the processor unit further comprises:

an internal memory arranged to store a portion of the complete counter values.

10. The processor unit of claim 9, wherein the portion is a scan line.

11. The processor unit of claim 9, wherein the portion is a tile.

12. A graphics processing device, comprising:

a display;

a processing unit for processing vector graphics primitives, and including;

counters configured to store a value indicating a current state of a fill rule for each of a sub-pixel sampling point for a pixel,

a bus for receiving instructions and data,

a first internal buffer configured to store at least one indicator bit value for each pixel,

a memory for storing data, and

determination logic configured to determine whether or not to retrieve and to retrieve the counter value from a memory based on the indicator bit values.

13. The handheld device of claim 12, wherein the processing unit further comprises:

a second internal buffer configured to store limited values for each counter,

wherein the determination logic is further configured to determine whether or not to retrieve the limited counter values from the second buffer.

14. The handheld device of claim 13, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has not changed.

15. The device of claim 13, wherein the indicator bits of the first buffer include a value for indicating that a value of the counter has to be retrieved from an external memory.

16. The device of claim 13, wherein the indicator bits of the first buffer include values for indicating a range of the second buffer from which the limited value of each counter is retrieved.

17. The device of claim 12, wherein the memory is an external memory configured to store counter values for each pixel to be processed, and the bus is a bi-directional bus configured to retrieve counter values from the external memory.

18. The device of claim 12, wherein the memory is an internal memory configured to store counter values for each pixel to be processed, and the bus is a unidirectional bus configured to receive instructions and data.

19. The device of claim 12, wherein a memory is configured to store complete counter values for each sub-pixel having a counter.

20. The device of claim 12, wherein the processor unit further comprises:

an internal memory arranged to store a portion of the complete counter values.

21. The device of claim 20, wherein the portion is a scan line.

22. The device of claim 20, wherein the portion is a tile.

23. The device of claim 12, wherein the device comprises a handheld device.