Daisy chain cascading devices

• US 20070109833A1
• Filed: 11/08/2006
• Published: 05/17/2007
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki, Oh, HakJune, Pyeon, Hong
• Granted Patent: US 9,240,227 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 13/4247 on a daisy chain bus
• CPC Class Codes: G06F 13/4256 using a clocked protocol
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data, address and command information, and control signals to the second device from the first device. The devices coupled in the daisy chain comprise a serial input (SI) and a serial output (SO). Information is input to a device via the SI. The information is output from the device via the SO. The SO of an earlier device in the daisy chain cascade is coupled to the SI of a device later in the daisy chain cascade. Information input to the earlier device via the device'"'"'s SI is passed through the device and output from the device via the device'"'"'s SO. The information is then transferred to the later device'"'"'s SI via the connection from the earlier device'"'"'s SO and the later device'"'"'s SI.

Claims

1. A semiconductor memory device comprising:

memory;

a serial data link interface configured to receive serial input data at a serial data input port, and to transfer serial output data to a serial data output port;

a control input for receiving a first input enable signal that is used to enable the memory device to process the serial input data;

a control output for outputting a second input enable signal; and

control circuitry responsive to the first input enable signal that controls data transfer between the serial data link interface and the memory bank.

2. The semiconductor memory device of claim 1, wherein the memory comprises a plurality of memory banks.

3. The semiconductor memory device of claim 1, wherein the second input enable signal is the first input signal delayed.

4. The semiconductor memory device of claim 1, wherein the second input enable signal is derived from the first input signal.

5. The semiconductor memory device of claim 1, wherein the data transfer occurs at a double data rate based on the rising and falling edges of a clock signal.

6. The semiconductor memory device of claim 1, wherein the serial data link interface is further configured to convert serial input data into parallel data and to transfer the data to the memory.

7. The semiconductor memory device of claim 6, wherein the serial data link interface is further configured to convert parallel data from the memory into serial output data.

8. The semiconductor memory device of claim 1, wherein the control circuitry is configured to receive executable instructions at the serial input port to control the transfer of serial input and output data to and from the memory.

9. The semiconductor memory device of claim 8 further comprising a unique device identification number.

10. The semiconductor memory device of claim 9, wherein the control circuitry controls the access of the memory in response to target device address corresponding to the unique device identification number associated with the device, the target device address being contained in a target device address field of the serial input data.

11. The semiconductor memory device of claim 8, wherein the control circuitry controls the transfer of the data to the location in the memory identified in an address field of the serial input data.

12. The semiconductor memory device of claim 1, wherein the memory, the serial data link interface and the control circuitry are located within a single package having a one-side pad architecture.

13. The semiconductor memory device of claim 1, wherein the memory comprises a non-volatile memory bank.

14. The semiconductor memory device of claim 13, wherein the non-volatile memory bank is a flash memory bank.

15. The semiconductor memory device of claim 14, wherein the non-volatile memory bank is a NAND flash memory bank.

16. The semiconductor memory device of claim 1 further comprising:

a second control input for receiving a first output enable signal that is used to enable the memory device to send serial output data to an external device; and

a second control output for outputting a second output enable signal.

17. A method of controlling data transfer between a serial link interface and a memory bank in a semiconductor memory device, the method comprising:

receiving a serial input data stream at a serial data link interface;

receiving a first input enable signal at a control input;

enabling the processing of serial input data based on the input enable signal to store data in or access data from memory;

sending a second input enable signal from a control output; and

sending a serial output data stream from the serial data link interface.

18. The method of claim 17 further comprising parsing the serial input data stream to extract a device address, a command, and a memory bank address of the memory bank.

19. The method of claim 17 wherein the command is a write command, and processing further includes:

converting the serial input data into parallel data; and

transferring the parallel data to the memory bank.

20. The method of claim 17 wherein the command is a read command, and processing further includes:

transferring parallel data between the memory bank and the serial data link interface; and

converting the parallel data into serial output data.

21. The method of claim 17 wherein the semiconductor memory device is a flash memory device.

22. The method of claim 17 wherein the flash memory device is a NAND device.

23. The flash memory system having a plurality of serially connected flash memory devices comprising:

a first flash memory device having a serial data input port, a serial data output port, a control input port, and a control output port, the first flash memory device configured to receive serial input data and an input enable signal from an external source device, and to send serial output data and a second input enable signal; and

a second flash memory device having a serial data input port, a serial data output port and a control input port, the second flash memory device configured to receive the serial output data of the first memory device as serial input data and the second input enable signal from the data first flash memory device at the control input port.

24. The flash memory system of claim 23 wherein the second input enable signal is the first input signal delayed.

25. The flash memory system of claim 23 wherein the second input enable signal is derived from the first input enable signal.

26. The flash memory system of claim 23 wherein the external source device is a controller.

27. The flash memory system of claim 23 wherein the external source device is a flash memory device.

28. The flash memory system of claim 23 wherein the second flash memory device further includes a control output port and is further configured to send serial output data and a third input enable signal to an external target device.

29. The flash memory system of claim 28 wherein each flash memory device of the plurality of flash memory devices possesses a unique device identification number.

30. The flash memory system of claim 29 wherein each flash memory device of the plurality of flash memory devices is configured to parse a target device address field of serial input data to determine whether the device is the target device by correlating the target device address with the unique device identification number of the device.

31. The flash memory system of claim 30 wherein each flash memory device of the plurality of flash memory devices is further configured to parse the target device address field prior to processing any additional serial input data received.

32. The flash memory system of claim 31 where each of the plurality of flash memory devices is further configured to ignore the serial input data if the memory device is not the target device.

33. The flash memory system of claim 23, wherein:

the first flash memory device further includes a second control input port and a second control output port, and is configured to receive an output enable signal from an external source device, and to send a second output enable signal; and

the second flash memory device further includes a second control input port, and is configured to receive the second output enable signal from the data first flash memory device.

34. The flash memory system of claim 23, wherein a single clock signal is communicated in a cascading signal to each flash memory device of the plurality of serially connected flash memory devices.

35. The flash memory system of claim 23, wherein a single clock signal is communicated to each of the plurality of serially connected flash memory devices, and the output of the flash memory system is delayed by a predetermined latency.

36. The flash memory system of claim 23 wherein each of the plurality of flash memory devices further include:

a flash memory bank

a serial data link interface configured to receive serial input data at an serial data input port and transfer the serial input data to the memory bank, and to transfer serial output data to a serial data output port; and

control circuitry that controls data transfer between the serial data link interface and the flash memory bank, and between the serial data link interface and the serial data output port.

37. The flash memory system of claim 36 wherein the flash memory bank is a NAND flash memory.

38. A semiconductor memory device comprising:

memory;

a unique device identification number;

a serial data link interface configured to receive serial input data at a serial data input port; and

control circuitry responsive to a target device address field in the serial input data that correlates with the unique device identification number to control access to the memory bank.

39. The semiconductor memory of claim 38 wherein the memory comprises a plurality of memory banks.

40. The semiconductor memory of claim 38 wherein:

the serial data link is further configured to transfer serial output data to a serial data output port, the serial input data and serial output data containing target device address information; and

the control circuitry is configured to control data transfer between the serial data link interface and the memory bank, and between the serial data link interface and the serial data output port.

41. The semiconductor memory device of claim 40, wherein the data transfer occurs at a double data rate based on the rising and falling edges of a clock signal.

42. The semiconductor memory device of claim 40, wherein the serial data link interface is further configured to convert serial input data into parallel data and to transfer the data to the memory bank.

43. The semiconductor memory device of claim 42, wherein the serial data link interface is further configured to convert parallel data from the memory bank into serial output data.

44. The semiconductor memory device of claim 43, wherein the control circuitry is configured to receive executable instructions to control the transfer of serial input and output data to and from the memory bank.

45. The semiconductor memory device of claim 38, wherein the control circuitry is programmed with executable instructions to parse the target device address field of serial input data and to control the transfer of the data to the location in the memory bank identified in an address field.

46. The semiconductor memory device of claim 38, wherein the memory bank, the serial data link interface and the control circuitry are located within a single package having a one-side pad architecture.

47. The semiconductor memory device of claim 38, wherein the memory bank comprises a non-volatile memory bank.

48. The semiconductor memory device of claim 47, wherein the non-volatile memory bank is a flash memory bank.

49. The semiconductor memory device of claim 47, wherein the non-volatile memory bank is a NAND flash memory bank.

50. A method of controlling data transfer between a serial link interface and a memory bank in a semiconductor memory device, the method comprising:

receiving a serial input data stream at a serial data link interface, the serial input data stream including target device address, command, and memory bank address information;

parsing the serial input data stream to extract a target device address, a command, and a memory bank address of the memory bank; and

processing the serial input data stream if the target device address correlates with a unique device identifier.

51. The method of claim 50 further comprising sending a serial output data stream from the serial data link interface.

52. The method of claim 50 wherein the command is a write command, and processing further includes:

converting the serial input data into parallel data; and

transferring the parallel data to the memory bank.

53. The method of claim 50 wherein the command is a read command, and processing further includes:

transferring parallel data between the memory bank and the serial data link interface; and

converting the parallel data into serial output data.

54. The method of claim 50 wherein the semiconductor memory device is a flash memory device.

55. The method of claim 50 wherein the semiconductor memory device is a NAND device.

56. The memory system having a plurality of serially connected flash memory devices comprising:

a first memory device having;

(a) memory,

(b) a unique device identifier,

(c) a serial data input port,

(d) a serial data output port,

the first memory device configured to receive serial input data at the serial data input port from an external source device and to send serial output data from the serial data output port, the serial input data and serial output data containing target device address information, and further configured to process the serial input data if the target device address correlates with a unique device identifier; and

a second memory device having;

(a) a unique device identifier,

(b) a serial data input port, in communication with the serial data output port of the first memory device, and

(c) a serial data output port,

the second memory device configured to receive serial output data of the data first memory device at the serial data input port of the second device and to process the serial input data if the target device address correlates with a unique device identifier.

57. The memory system of claim 56 wherein the external source device is a controller.

58. The memory system of claim 56 wherein the external source device is a memory device.

59. The memory system of claim 56 wherein the second memory device is further configured to send serial output data to an external target device.

60. The memory system of claim 56 wherein each memory device of the plurality of memory devices is further configured to bypass the serial data without processing if the target device address does not correlate with unique device identifier.

61. The memory system of claim 56 wherein the memory is a flash memory.

62. The memory system of claim 56 wherein the memory is a NAND flash memory.