NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME

• US 20070109848A1
• Filed: 10/27/2006
• Published: 05/17/2007
• Est. Priority Date: 11/15/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sato, Atsuhiro, Sugimae, Kikuko, Ichige, Masayuki, Arai, Fumitaka, Matsunaga, Yasuhiko
• Granted Patent: US 7,705,394 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, a first and a second control gate electrode layer, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture, a third and a fourth control gate electrode layer, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture, a fifth and a sixth control gate electrode layer, and a third metallic silicide film; and a liner insulating film directly disposed on a first source and drain region of the memory cell transistor, a second source and drain region of the low voltage transistor, and a third source and drain region of the high voltage transistor.

Claims

1. A nonvolatile semiconductor memory comprising:

a cell array region including a memory cell transistor, which comprises;

first source and drain regions, a first tunneling insulating film formed on a semiconductor region between the first source and drain regions, a first floating gate electrode layer formed on the first tunneling insulating film, a first inter-gate insulating film formed on the first floating gate electrode layer, a first control gate electrode layer formed on the first inter-gate insulating film, a second control gate electrode layer formed on the first control gate electrode layer, and a first metallic silicide film electrically connected to the second control gate electrode layer;

a high voltage circuit region that is disposed around the cell array region and comprises;

a high voltage transistor, which comprises second source and drain regions, a high voltage gate insulating film formed on a semiconductor region between the second source and drain regions, a high voltage gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture formed on the high voltage gate electrode layer, a third control gate electrode layer formed on the second inter-gate insulating film, a fourth control gate electrode layer formed on the third control gate electrode layer, and a second metallic silicide film electrically connected to the fourth control gate electrode layer;

a low voltage circuit region that is disposed in a different area from the high voltage circuit region, which is around the cell array region, and comprises;

a low voltage transistor that comprises third source and drain regions, a second tunneling insulating film formed on a semiconductor region between the third source and drain regions, a second floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture formed on the second floating gate electrode layer, a fifth control gate electrode layer formed on the third inter-gate insulating film, a sixth control gate electrode layer formed on the fifth control gate electrode layer, and a third metallic silicide film electrically connected to the sixth control gate electrode layer; and

a liner insulating film directly disposed on the first source and drain regions, the second source and drain regions, and the third source and drain regions.

2. The nonvolatile semiconductor memory of claim 1, further comprising a barrier insulating film that is connected to a part of the liner insulating film and disposed on the first source and drain regions, the second source and drain regions, and the third source and drain regions.

3. The nonvolatile semiconductor memory of claim 2, wherein the barrier insulating film is further disposed on the first metallic silicide film, the second metallic silicide film, and the third metallic silicide film.

4. The nonvolatile semiconductor memory of claim 2, wherein the value of the height from the surface of a semiconductor substrate in which the first through the third source and drain regions are formed to the barrier insulating film is greater than the value of the height from the surface of the semiconductor substrate in which the first through the third source and drain regions are formed until the first through the third inter-gate insulating films.

5. The nonvolatile semiconductor memory of claim 3, wherein the value of the height from the surface of a semiconductor substrate in which the first through the third source and drain regions are formed to the barrier insulating film is greater than the value of the height from the surface of the semiconductor substrate in which the first through the third source and drain regions are formed until the first through the third inter-gate insulating films.

6. The nonvolatile semiconductor memory of claim 1, wherein the high voltage gate insulating film is thicker than the first and second tunneling insulating films.

7. The nonvolatile semiconductor memory of claim 1, wherein the liner insulating film is a nitride film.

8. The nonvolatile semiconductor memory of claim 1, wherein the first through the third metallic silicide films are one of cobalt silicide and nickel silicide.

9. The nonvolatile semiconductor memory of claim 2, further comprising:

a first interlayer insulating film disposed between the liner insulating film and the barrier insulating film.

10. The nonvolatile semiconductor memory of claim 2, wherein the barrier insulating film is a nitride film.

11. A nonvolatile semiconductor memory comprising:

a cell array region including a memory cell transistor, which comprises first source and drain regions, a first tunneling insulating film formed on a semiconductor region between the first source and drain regions, a first floating gate electrode layer formed on the first tunneling insulating film, a first inter-gate insulating film formed on the first floating gate electrode layer, a first control gate electrode layer formed on the first inter-gate insulating film, a second control gate electrode layer formed on the first control gate electrode layer, and a first metallic silicide film electrically connected to the second control gate electrode layer;

a high voltage circuit region that is disposed around the cell array region, in a recessed semiconductor substrate having a lower surface than the semiconductor substrate disposing the first source and drain regions, and includes a high voltage transistor, which comprises second source and drain regions, a high voltage gate insulating film formed on a semiconductor region between the second source and drain regions, a second floating gate electrode layer formed on the high voltage gate insulating film, a second inter-gate insulating film having an aperture formed on the second floating gate electrode layer, a third control gate electrode layer formed on the second inter-gate insulating film, a fourth control gate electrode layer formed on the third control gate electrode layer, and a second metallic silicide film electrically connected to the fourth control gate electrode layer;

a low voltage circuit region that is disposed in a different area from the high voltage circuit region, which is around the cell array region, and includes a low voltage transistor that comprises third source and drain regions, a second tunneling insulating film formed on a semiconductor region between the third source and drain regions, a third floating gate electrode layer formed on the second tunneling insulating film, a third inter-gate insulating film having an aperture formed on the third floating gate electrode layer, a fifth control gate electrode layer formed on the third inter-gate insulating film, a sixth control gate electrode layer formed on the fifth control gate electrode layer, and a third metallic silicide film electrically connected to the sixth control gate electrode layer; and

a liner insulating film directly disposed on the first source and drain regions, the second source and drain regions, and the third source and drain regions,

wherein the thickness of the high voltage gate insulating film is greater than thickness of the first and the second tunneling insulating films, and the surface of the high voltage gate insulating film and surface of the first and the second tunneling insulating film are flat.

12. The nonvolatile semiconductor memory of claim 11, further comprising a barrier insulating film that is connected to a part of the liner insulating film and disposed on the first source and drain regions, the second source and drain regions, and the third source and drain regions.

13. The nonvolatile semiconductor memory of claim 12, wherein a barrier insulating film is further disposed on the first metallic silicide film, the second metallic silicide film, and the third metallic silicide film.

14. The nonvolatile semiconductor memory of claim 12, wherein the value of the height from the surface of a semiconductor substrate in which the first through the third source and drain regions are formed to the barrier insulating film is greater than the value of the height from the surface of the semiconductor substrate in which the first through the third source and drain regions are formed until the first through the third inter-gate insulating films.

15. The nonvolatile semiconductor memory of claim 13, wherein the value of the height from the surface of a semiconductor substrate in which the first through the third source and drain regions are formed to the barrier insulating film is greater than the value of the height from the surface of the semiconductor substrate in which the first through the third source and drain regions are formed until the first through the third inter-gate insulating films.

16. The nonvolatile semiconductor memory of claim 11, wherein the liner insulating film is a nitride film.

17. The nonvolatile semiconductor memory of claim 11, wherein the first through the third metallic silicide films are one of cobalt silicide and nickel silicide.

18. The nonvolatile semiconductor memory of claim 12, further comprising:

a first interlayer insulating film disposed between the liner insulating film and the barrier insulating film.

19. A fabrication method for a nonvolatile semiconductor memory, which includes a cell array region, a high-voltage circuit region, and a low-voltage circuit region, the fabrication method comprising:

depositing a tunneling insulating film on a semiconductor substrate, a floating gate electrode layer on the tunneling insulating film, and a first stopper film on the floating gate electrode layer in the cell array region, the high-voltage circuit region, and the low-voltage circuit region;

removing the first stopper film and the floating gate electrode layer in the high voltage region;

depositing a high voltage gate insulating film on the semiconductor substrate, a high voltage gate electrode layer on the high voltage gate insulating film, and a second stopper film on the high voltage gate electrode layer in the high voltage region;

removing the second stopper film, the floating gate electrode layer, and the high voltage gate electrode layer in a prospective region, in which element isolating regions are to be formed, in the cell array region, the high-voltage circuit region, and the low-voltage circuit region;

removing the high voltage gate insulating film, and the tunneling insulating film in the prospective region in which element isolating regions are to be formed, in the cell array region, the high-voltage circuit region, and the low-voltage circuit region;

etching the semiconductor substrate until a depth at which the element isolating regions are to be formed and forming etching grooves in the semiconductor substrate in the cell array region, the high-voltage circuit region, and the low-voltage circuit region;

depositing an insulating film on the entire device surface including the cell array region, the high voltage transistor region, and the low voltage transistor region; and

filling the insulating film in the etching grooves and forming element isolating regions.

20. The fabrication method of claim 19, further comprising:

depositing a pad insulating film on the semiconductor substrate in the cell array region, the high voltage transistor region, and the low voltage transistor region;

depositing a nitride film on the pad insulating film in the cell array region, the high voltage transistor region, and the low voltage transistor region;

removing the nitride film on the pad insulating film in the high voltage transistor region;

forming a LOCOS insulating film in the high voltage transistor region; and

removing the nitride film, the LOCOS insulating film, and the pad insulating film;

forming the surface of the semiconductor substrate for the high voltage transistor region being lower than the surface of the semiconductor substrate for the cell array region and the low voltage transistor region by the difference between the thickness of the LOCOS insulating film and that of the pad insulating film.