Use of Data Latches in Cache Operations of Non-Volatile Memories
First Claim
1. A method of operating a non-volatile memory device which includes an array of memory cells and a set of read/write circuits for operating on a group of memory cells of said array in parallel, each read/write circuits having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells, the method comprising:
- performing a first operation on a first group of memory cells using a first data set stored in a first plurality of the sets of data latches; and
during said first operation, caching a second data set for a second operation in said first plurality of the sets of data latches.
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Accused Products
Abstract
Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.
86 Citations
12 Claims
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1. A method of operating a non-volatile memory device which includes an array of memory cells and a set of read/write circuits for operating on a group of memory cells of said array in parallel, each read/write circuits having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells, the method comprising:
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performing a first operation on a first group of memory cells using a first data set stored in a first plurality of the sets of data latches; and
during said first operation, caching a second data set for a second operation in said first plurality of the sets of data latches. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of operating a non-volatile memory device which includes an array of memory cells and a set of read/write circuits for operating on a group of memory cells of said array in parallel, each read/write circuits having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells, the method comprising:
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storing a first set of data for a first group of the memory cells into the corresponding sets of data latches;
writing the first set of data into said first group of memory cells, wherein the writing includes alternating program and verify phases;
pausing said writing between one of the program phases and one of the verify phases;
subsequent to said pausing, reading a second set of data from a second group of the memory cells into latches of said corresponding sets of data latches; and
subsequent to said reading, resuming the paused writing. - View Dependent Claims (11, 12)
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Specification