MEMORY DEVICE WITH IMPROVED WRITING CAPABILITIES

• US 20070109878A1
• Filed: 10/26/2006
• Published: 05/17/2007
• Est. Priority Date: 10/26/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Gouin, Vincent, Chanussot, Christophe
• Granted Patent: US 7,486,540 B2
• Time in Patent Office: Days
• US Class Current: 365/189.110
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

Method and memory device for reliably writing an information value to a memory element of the memory device. A first information value is represented by a first potential and a second information value is represented by a second potential. A bit line is provided for writing either the first information value or the second information value to the memory element. A potential controller is coupled to the bit line, where the potential controller is configured to apply a third potential to the bit line, which is less than the first potential when writing the first information value to the memory element.

Claims

1. A memory device, comprising:

a memory element for storing an information value selected from a first information value being represented by a first potential and a second information value being represented by a second potential, the first potential being less than the second potential;

a bit line for selectively writing the first information value or the second information value to the memory element; and

a potential controller coupled to the bit line, the potential controller being configured to apply a third potential to the bit line, which is less than the first potential when writing the first information value to the memory element.

2. The memory device according to claim 1, wherein the memory element is a volatile memory element storing either the first or the second information value when the first potential is applied to a first power supply terminal of the memory element and the second potential is applied to a second power supply terminal of the memory element.

3. The memory device according to claim 1, wherein the potential controller comprises a potential circuit coupled to the bit line, the potential circuit being configured to generate the first potential in response to a control signal.

4. The memory device according to claim 3, wherein the control signal comprises a pulse, the potential circuit being configured to generate the third potential in response to a falling edge of the pulse.

5. The memory device according to claim 4, wherein the potential circuit is configured to reduce the potential of the bit line to the first potential in response to a rising edge of the pulse during a first time interval and to apply the third potential to the bit line during a subsequent second time interval in response to a falling edge of the pulse.

6. The memory device according to claim 1, wherein the potential controller comprises a potential circuit coupled to the bit line for generating the third potential, the potential circuit comprising a transistor and a capacitor, the capacitor being coupled between a first terminal of the transistor and a control terminal of the transistor, the first terminal being coupled to the bit line.

7. The memory device according to claim 6, wherein the potential circuit comprises a delay element coupled between the control terminal of the transistor and the capacitor.

8. The memory device according to claim 6, wherein the potential circuit comprises a resistive element coupled in parallel to the transistor.

9. The memory device according to claim 8, wherein the resistive element is formed by a transistor.

10. The memory device according to claim 6, wherein the potential circuit comprises a diode coupled in parallel to the transistor, a cathode of the diode being coupled to the first terminal of the transistor.

11. The memory device according to claim 6, further comprising a further transistor coupled in parallel to the transistor, the further transistor being arranged to form a diode.

12. The memory device according to claim 6, comprising a further transistor coupled in parallel to the transistor, the further transistor being arranged to form a resistive element.

13. The memory device according to claim 6, wherein the potential controller is configured to apply a pulse to the control terminal of the transistor, the potential circuit being configured to generate the third potential in response to the pulse.

14. The memory device according to claim 13, wherein the potential circuit comprises a further transistor having a first terminal, a second terminal and a control terminal, the second terminal of the further transistor being coupled to the first terminal of the transistor, the potential controller being configured to apply a further pulse to the control terminal, the further pulse being longer than the pulse.

15. The memory device according to claim 1, further comprising a further bit line for writing either the first information value or the second information value to the memory element, the potential controller being further coupled to the further bit line, the potential controller being configured to apply the third potential to the further bit line when writing the second information value to the memory element.

16. The memory device according to claim 15, wherein the potential controller comprises a potential circuit coupled to the bit line for generating the third potential when writing the first information value to the memory element and a further potential circuit coupled to the further bit line for generating the third potential.

17. The memory device according to claim 15, wherein the potential controller is configured to activate only the potential circuit or to activate only the further potential circuit at a given time same time.

18. The memory device according to claim 15, wherein the potential controller is configured to apply the third potential to the bit line and to apply the second potential to the further bit line when writing the first information value to the memory element, and to apply the second potential to the bit line and the third potential to the further bit line when writing the second information value to the memory element.

19. The memory device according to claim 1, wherein the potential controller is figured to apply the second potential to the bit line when writing the second information value to the memory element.

20. The memory device according to claim 1, wherein the potential controller is configured to apply a fourth potential to the bit line when writing the second information value to the memory element, the fourth potential being greater than the second potential.

21. A memory device, comprising:

a memory element for storing an information value selected from a first information value being represented by a first potential and a second information value being represented by a second potential, the first potential being less than the second potential;

a bit line for writing either the first information value or the second information value to the memory element; and

a potential controller coupled to the bit line, the potential controller being configured to apply a third potential to the bit line, which is greater than the second potential when writing the second information value to the memory element.

22. A method for writing either a first information value or a second information value via a bit line to a memory element, the first information value being represented by a first potential, the second information value being represented by a second potential, the method comprising:

applying a third potential to the bit line when writing the first information value to the memory element, the third potential being less than the first potential.

23. A method for writing either a first information value or a second information value via a bit line to a memory element, the first information value being represented by a first potential, the second information value being represented by a second potential, the method comprising:

applying a third potential to the bit line when writing the second information value to the memory element, the third potential being greater than the second potential.