Configurable de-interleaver design
First Claim
1. A method for processing and de-interleaving a received signal, comprising:
- receiving a continuous wave radio frequency signal and front end processing the radio frequency signal to filter, amplify and down-convert the radio frequency signal to produce a down-converted ingoing signal;
converting the ingoing signal from a time domain signal to a frequency domain signal wherein the frequency domain signal comprises a plurality of tones arranged in a first sequence;
tone de-interleaving the plurality of tones by re-arranging the first sequence of tones into a second sequence;
producing a specified number of tones from the second sequence to a corresponding specified number of detector arrays that are each operable to generate a bit stream portion therefrom; and
combining the bit steam portions produced by the detector array to create an ingoing bit stream;
bit de-interleaving the ingoing bit stream to create a de-interleaved bit stream that, without transmission interference, matches an outgoing bit stream in a transmitter prior to scrambling and interleaving by the transmitter that generated the received signal.
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Accused Products
Abstract
An integrated circuit radio transceiver and method therefor is operable to flexibly and efficiently de-interleave a received communication signal by initially changing a received signal from the time domain to the frequency domain to generate a plurality of tones that are then rearranged in a first de-interleaving step to an order expected by a downstream decoder. Thereafter, the tones are detected to generate a soft bit sequence and are then reverse-swizzled and de-interleaved. The de-interleaving step is performed in a manner that compensates for row/column offset interleaving performed by a transmitter that transmitted the received signal being processed.
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Citations
24 Claims
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1. A method for processing and de-interleaving a received signal, comprising:
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receiving a continuous wave radio frequency signal and front end processing the radio frequency signal to filter, amplify and down-convert the radio frequency signal to produce a down-converted ingoing signal;
converting the ingoing signal from a time domain signal to a frequency domain signal wherein the frequency domain signal comprises a plurality of tones arranged in a first sequence;
tone de-interleaving the plurality of tones by re-arranging the first sequence of tones into a second sequence;
producing a specified number of tones from the second sequence to a corresponding specified number of detector arrays that are each operable to generate a bit stream portion therefrom; and
combining the bit steam portions produced by the detector array to create an ingoing bit stream;
bit de-interleaving the ingoing bit stream to create a de-interleaved bit stream that, without transmission interference, matches an outgoing bit stream in a transmitter prior to scrambling and interleaving by the transmitter that generated the received signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. Circuitry for processing and de-interleaving a received signal, which received signal was scrambled and interleaved by a transmitter, comprising:
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tone de-interleaving circuitry for receiving a first sequence of tones and for rearranging the first sequence of tones into a second sequence of tones, which rearranging to produce the second sequence of tones operably compensates for the scrambling performed by the transmitter and arranges the tones in an order expected by a downstream decoder;
logic for selecting a number of tones from the second sequence of tones for detection to generate a soft bit sequence;
a plurality of detector array circuits each operable to produce a bit sequence from a selected tone, wherein the number of the plurality of detector array circuits corresponds to the number of tones selected from the second sequence of tones wherein each of the plurality of detector array circuits receives one of the tones selected from the second sequence of tones; and
de-interleaving circuitry to de-interleave bit sequences produced by the number of the plurality of detector array circuits. - View Dependent Claims (10, 11, 12, 13, 14)
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15. Circuitry for processing and de-interleaving a received signal, comprising:
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de-interleaving circuitry to de-interleave received bit sequences produced by a number of detector array circuits wherein the de-interleaving circuitry further includes a plurality of block de-interleaving circuit paths that correspond to a number of interleaving circuit paths used by a transmitter that generated the received signal; and
wherein the de-interleaving circuitry includes logic to generate a table that is sized the same as an interleaving table of interleaving circuitry of a transmitter and further wherein the de-interleaving circuitry begins to extract bits from the table from an offset location that corresponds to an offset location utilized within the transmitter to interleave the bits prior to transmission. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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Specification