METHOD OF DEFINING SEMICONDUCTOR FABRICATION PROCESS UTILIZING TRANSISTOR INVERTER DELAY PERIOD

• US 20070110194A1
• Filed: 10/19/2006
• Published: 05/17/2007
• Est. Priority Date: 10/19/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Leipold, Dirk, de Obaldia, Elida, Staszewski, Robert
• Granted Patent: US 7,813,462 B2
• Time in Patent Office: Days
• US Class Current: 375/345
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/1806 the frequency divider comprising a phase accumulator generating the frequency divided signal
• CPC Class Codes: H04L 27/361 Modulation using a single or unspecified number of carriers, e.g. with separate stages of phase and amplitude modulation

Abstract

A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The method and apparatus provide direct measurement of fabrication process variation in circuits without requiring any additional test equipment by utilizing a time to digital converter (TDC) circuit already present in the chip. The TDC circuit relies on the time delay in an inverter chain to sample a high speed CKV clock using a slow FREF clock. Calculation of inverse time provides a direct correlation for fabrication process variation in each die.

Claims

1. A method of compensating an analog circuit for integrated circuit process variation, said method comprising the steps of:

measuring a time delay of an inverter fabricated on said integrated circuit; and

adjusting settings of said analog circuit in accordance with said measured time delay.

2. The device according to claim 1, wherein said inverter is part of a time to digital converter (TDC) circuit.

3. The device according to claim 1, further comprising a step of writing a digital representation of said time delay onto said integrated circuit.

4. The device according to claim 2, wherein said digital representation comprises 2-bits adapted to indicate one of weak, nominal and strong process variation readings.

5. A method of compensating a plurality of analog and radio frequency (RF) circuits for integrated circuit process variation, said method comprising the steps of:

measuring a time delay of an inverter fabricated on said integrated circuit;

generating a digital indication of process variation corresponding to said time delay;

permanently burning said digital indication into said integrated circuit; and

reading said digital indication and adjusting settings of said analog and RF circuits in accordance with said digital indication.

6. The device according to claim 5, wherein said inverter is part of a time to digital converter (TDC) circuit.

7. The device according to claim 5, wherein said digital indication comprises a 2-bit number adapted to indicate one of three possible indications, including weak, nominal and strong process corner.

8. A System on a Chip (SoC), comprising:

an inverter chain fabricated on said SoC;

a time delay measurement circuit operative to measure a cell time delay of said inverter chain;

a burn in circuit operative to generate a digital indication of process variation corresponding to said time delay and to permanently burn said digital indication into said SoC;

means for retrieving said burned-in digital indication of process variation; and

means for periodically obtaining updated time delay measurements from said time delay measurement circuit and for comparing said updated time delay measurements with previous time delay measurements to yield an indication of current temperature therefrom.

9. The SoC according to claim 8, wherein said digital inverter chain comprises a time to digital converter (TDC) circuit.

10. The device according to claim 8, wherein said digital indication comprises a 2-bit number adapted to indicate one of three possible indications, including weak, nominal and strong process variation.

11. A process strength measurement device, comprising:

an inverter chain normally operative to determine a delay difference between a reference clock and a high speed clock;

a normalization circuit operative to accumulate said delay difference over a plurality of reference clock cycles to yield an average delay difference; and

means for calculating a measure of process strength as a function of said average fractional delay difference.

12. The device according to claim 11, wherein said means for calculating comprises means for comparing said average delay differences against desired thresholds for weak, baseline and strong process variations thereby providing said measure of process strength.

13. An apparatus for measuring process variation in an all digital phase locked loop (ADPLL), comprising:

a time to digital converter (TDC) circuit comprising a chain of inverters operative to generate a plurality of clock delay difference measurements; and

means for generating an indication of process strength as a function of said plurality of clock delay difference measurements.

14. The device according to claim 13, wherein said means for generating comprises means for comparing said plurality of clock delay difference measurements against desired thresholds for weak, baseline and strong process variations.

15. An apparatus for measuring process variation in a digital signal processor (DSP) having a clock retiming circuit including inverters and registers for comparing a system clock and a reference clock, comprising:

means for reading said registers in said clock retiming circuit;

means for determining the inverse of the clock adjustment provided by the clock retiming circuit; and

outputting retiming data which directly correlates with process variation of the DSP.

16. An apparatus for measuring process variation in a digital RF processor (DRP) having a clock retiming circuit including an inverter chain and corresponding registers for comparing a system clock and a reference clock, comprising:

means for reading said registers in said clock retiming circuit and determining an inverter delay therefrom; and

outputting retiming data which is directly proportional to process variation of core transistors making up said DRP.

17. A method of directly measuring process variation in a device incorporating a time to digital converter (TDC) circuit, said method comprising the steps of:

determining a number of transistors activated in a chain of inverters which matches the retiming of an external reference clock;

translating said number of transistors activated to an inverter delay period corresponding to said transistors; and

correlating said inverter delay period to yield a measurement of process variation.

18. A method of compensating performance of an analog circuit fabricated on an integrated circuit for variations in fabrication process technology, said method comprising the steps of:

measuring a statistic of a circuit fabricated on said integrated circuit and unrelated to said analog circuit; and

adjusting settings of said analog circuit in accordance with said measured statistic.

19. A method of claim 18, wherein said step of measuring comprises the step of estimating a delay time of an inverter.

20. A method of claim 18, wherein said step of measuring comprises the step of estimating a frequency step of a digitally controlled oscillator (DCO).

21. A method of claim 18, wherein said statistic is measured using fully digital techniques.