Ternary and Multi-Value Digital Signal Scramblers, Descramblers and Sequence of Generators

• US 20070110229A1
• Filed: 01/02/2007
• Published: 05/17/2007
• Est. Priority Date: 02/25/2004
• Status: Abandoned Application

• Current Assignee: Ternarylogic LLC
• Original Assignee: Ternarylogic LLC
• Inventors: Lablans, Peter
• Application Number:
  US11/618,986
• Publication Number:
  US 20070110229A1
• Time in Patent Office: Days
• US Class Current: 380/28
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.

Claims

1. An apparatus for evaluating an u^P valued arithmetical expression z=(r×

x)+(q×

y) wherein ×

is a multiplication defined in GF(u^P) and + is an addition defined in GF(u^P), with u≧

2 and p≧

1 except u^P=2, which can be represented by a u^P valued truth table, x and y are variables that can each assume one of u^P values and r and q are constants each of which is assigned one of (u^P−

1) values not including 0, and z is a result of the u^P valued expression, comprising;

a device with a first input enabled for receiving a signal representing variable x and a second input enabled for receiving a signal representing variable y and an output;

the device implementing a switching function sc4 with an u^P-valued truth table different from the truth table of the addition; and

the output enabled to provide a signal representing z.

2. The apparatus as claimed in claim 1, wherein:

an u^P-valued expression (r×

x) can be represented by a first u^P-valued inverter;

an u^P-valued expression (q×

y) can be represented by a second u^P-valued inverter; and

the truth table of the u^P-valued function sc4 can be created by modifying the truth table of the addition according to the first and the second inverter.

3. The apparatus as claimed in claim 2, wherein an u^P-valued expression (x×

r) can also be represented by the first u^P-valued inverter.

4. The apparatus as claimed in claim 1, wherein the apparatus is part of an u^P-valued Linear Feedback Shift Register (LFSR).

5. The apparatus as claimed in claim 2, wherein either the first or the second u^P-valued inverter is a unity inverter.

6. A method for physically evaluating an n-valued arithmetical expression z=(x×

r)+(y×

q), with n≧

3, x and y being n-valued variables of which each can assume one of n values, r and q being n-valued constants each of which is assigned one of (n−

1) values not including 0, with n-valued arithmetical functions × and

+, with ×

being a multiplication and with + being an addition defined in a Finite Field GF(n=u^P) with u≧

2 and p≧

1, and wherein the addition can be defined by a n-valued truth table comprising, executing a n-state switching expression (x sc4 y), wherein sc4 is an n-state switching function with a truth table that is different from the truth table of the addition.

7. The method as claimed in claim 6, further comprising:

applying the method for implementing an n-valued Linear Feedback Shift Register.

8. The method as claimed in claim 6, further comprising:

assigning r=1 to the n-valued expression, making it z=x+(y×

q).

9. The method as claimed in claim 6, further comprising:

assigning q=1 to the n-valued expression, making it z=(x×

r)+y.

10. A method for implementing an Linear Feedback Shift Register (LFSR) that can be described by a n-valued irreducible polynomial over GF(n=u^P) with u≧

2 and p≧

1 except u^P=2 that includes executing at least one n-valued expression (r×

x)+(q×

y) wherein x and y are n-valued variables, r and q are n-valued constants and ×

is a commutative multiplication defined in GF(n=u^P), and + is a n-valued addition defined in GF(n=u^P) which can be represented by an n-valued truth table, comprising;

evaluating an n-valued expression (x sc4 y), wherein sc4 is a n-valued switching function which can be represented by a n-valued truth table that is different from the truth table of the addition.

11. The method as claimed in claim 10, wherein the irreducible polynomial is primitive.

12. The method as claimed in claim 10, wherein (r×

x)=x.

13. The method as claimed in claim 10, wherein (q×

y)=y.

14. The method as claimed in claim 10, further comprising using the LFSR for generating a sequence of n-valued symbols.

15. The method as claimed in claim 10, further comprising using the LFSR for scrambling a sequence of n-valued symbols.

16. The method as claimed in claim 10, further comprising using the LFSR for descrambling a sequence of n-valued symbols.

17. A method for physically evaluating an n-valued logic expression (x sc1 r) sc2 (y sc3 q) with n≧

3, wherein x and y are n-valued variables, r and q are n-valued constants and sc1, sc2 and sc3 are n-valued switching functions which can be represented by n-valued truth tables, comprising;

creating a n-valued switching function sc4 with a truth table by modifying the truth table of function sc2 according to a first inverter representing (x sc1 r) and a second inverter representing (y sc3 q);

implementing the n-valued switching function sc4 in a device with a first input, a second input and an output;

providing signals representing n-valued variables x and y to the device; and

generating a signal representing z=(x sc4 y) on an output of the device.

18. The method as claimed in claim 17, further comprising:

reducing the expression (x sc1 r) sc2 (y sc3 q) to an n-valued expression ((x sc1 r) sc5 y) wherein sc5 is an n-valued switching function which can be represented by an n-valued truth table which can be created by modifying the truth table of sc2 according to a second n-valued inverter representing (y sc3 q); and

reducing the n-valued expression ((x sc1 r) sc5 y) to the n-valued expression (x sc4 y) wherein sc4 can be represented by an n-valued truth table which can be created by modifying the truth table of sc5 according to a first n-valued inverter representing (x sc1 r).

19. The method as claimed in claim 18, further comprising the steps:

selecting a first element of the second n-valued inverter representing (y sc3 q);

selecting in the truth table of sc2 a column corresponding with an input equal to the first element of the second inverter of the previous step;

placing the selected column of the truth table of sc2 in the previous step in the truth table of the n-valued switching function sc5 in the column position corresponding to the position of the element in the second inverter;

selecting a next element of the second n-valued inverter as the first element; and

repeating the previous three steps until all n elements of the second n-valued inverter have been evaluated.

20. The method as claimed in claim 19, further comprising the steps:

selecting a first element of the first n-valued inverter representing (x sc1 p);

selecting in the truth table of sc5 a row corresponding with an input equal to the first element of the inverter of the previous step;

placing the selected row of sc5 of the previous step in the truth table of n-valued switching function sc4 in the row position corresponding to the position of the element in the first inverter;

selecting a next element of the first n-valued inverter as the first element; and

repeating the previous three steps until all n elements of the first inverter have been evaluated.