Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
First Claim
1. A method of metal bonding vertically stacked wafer pairs comprising:
- forming a first wafer pair, including bonding a metallic line disposed on an ILD on a front side of a first wafer to a corresponding metallic line disposed on an ILD on a front side of a second wafer;
forming a second wafer pair, including bonding a metallic line disposed on an ILD on a front side of a third wafer to a corresponding metallic line disposed on an ILD on a front side of a fourth wafer;
providing a first metal bonding area at a back side of the second wafer and a second metal bonding area at a back side of the third wafer, said providing including forming an Si via through an active layer at a back side of the second wafer, wherein a first end of the Si via connects to the metallic line of the second wafer and a second end of the Si via is exposed at the back side of the second wafer;
increasing the first and second metal bonding areas; and
bonding the increased first metal bonding area to the increased second metal bonding area.
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Abstract
A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.
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Citations
20 Claims
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1. A method of metal bonding vertically stacked wafer pairs comprising:
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forming a first wafer pair, including bonding a metallic line disposed on an ILD on a front side of a first wafer to a corresponding metallic line disposed on an ILD on a front side of a second wafer;
forming a second wafer pair, including bonding a metallic line disposed on an ILD on a front side of a third wafer to a corresponding metallic line disposed on an ILD on a front side of a fourth wafer;
providing a first metal bonding area at a back side of the second wafer and a second metal bonding area at a back side of the third wafer, said providing including forming an Si via through an active layer at a back side of the second wafer, wherein a first end of the Si via connects to the metallic line of the second wafer and a second end of the Si via is exposed at the back side of the second wafer;
increasing the first and second metal bonding areas; and
bonding the increased first metal bonding area to the increased second metal bonding area. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of metal bonding multiple vertically stacked wafers comprising:
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depositing a first metallic line on an ILD of a front side of a first wafer;
depositing a second metallic line on an ILD of a front side of a second wafer;
bonding the first metallic line to the second metallic line;
depositing a third metallic line on an ILD of a front side of a third wafer;
depositing a fourth metallic line on an ILD of a front side of a fourth wafer;
bonding the third metallic line to the fourth metallic line;
forming a first Si via through an active layer at a back side of the second wafer, the first Si via having an internal end connected to the second metallic line and an external end exposed at the back side of the second wafer;
forming a second Si via through an active layer at a back side of the third wafer, the second Si via having an internal end connected to the third metallic line and an external end exposed at the back side of the third wafer;
increasing areas of the external ends of the first and second Si vias; and
bonding the areas. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 18)
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17. A method of metal bonding back sides of two wafers comprising:
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forming a first Si via through an active layer at a back side of a first wafer, wherein a first end of the first Si via is exposed;
forming a second Si via through an active layer at a back side of a second wafer, wherein a second end of the second Si via is exposed;
increasing areas of the first end and second end; and
bonding the increased areas. - View Dependent Claims (19, 20)
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Specification