Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices

• US 20070111386A1
• Filed: 11/21/2006
• Published: 05/17/2007
• Est. Priority Date: 02/20/2002
• Status: Abandoned Application

• Current Assignee: R List, Sarah Kim, Scot Kellar
• Original Assignee: R List, Sarah Kim, Scot Kellar
• Inventors: List, R., Kim, Sarah, Kellar, Scot
• Application Number:
  US11/603,521
• Publication Number:
  US 20070111386A1
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

Claims

1. A method of metal bonding vertically stacked wafer pairs comprising:

forming a first wafer pair, including bonding a metallic line disposed on an ILD on a front side of a first wafer to a corresponding metallic line disposed on an ILD on a front side of a second wafer;

forming a second wafer pair, including bonding a metallic line disposed on an ILD on a front side of a third wafer to a corresponding metallic line disposed on an ILD on a front side of a fourth wafer;

providing a first metal bonding area at a back side of the second wafer and a second metal bonding area at a back side of the third wafer, said providing including forming an Si via through an active layer at a back side of the second wafer, wherein a first end of the Si via connects to the metallic line of the second wafer and a second end of the Si via is exposed at the back side of the second wafer;

increasing the first and second metal bonding areas; and

bonding the increased first metal bonding area to the increased second metal bonding area.

2. The method of claim 1, wherein increasing the metal bonding areas comprises:

increasing a horizontal cross-sectional area of the second end of the Si via.

3. The method of claim 2, wherein increasing the horizontal cross-sectional area comprises:

forming an upper trench section in the back side of the second wafer, the upper trench section filled with a conductive material and connected to the Si via.

4. The method of claim 2, wherein increasing the horizontal cross-sectional area comprises:

etching the first Si via to form a tapered via.

5. The method of claim 1, wherein increasing the metal bonding areas comprises:

forming a dummy Si via in the active layer of the second wafer and a corresponding dummy Si via in the active layer of the third wafer.

6. The method of claim 5, wherein forming each dummy Si via comprises forming each dummy Si via to have a diameter smaller than a diameter of the first Si via.

7. The method of claim 1, further comprising:

thinning the back side of the second wafer.

8. The method of claim 1, further comprising:

forming a microprocessor in the first wafer;

forming a memory device in the second wafer; and

forming a communication device in the third or fourth wafer.

9. A method of metal bonding multiple vertically stacked wafers comprising:

depositing a first metallic line on an ILD of a front side of a first wafer;

depositing a second metallic line on an ILD of a front side of a second wafer;

bonding the first metallic line to the second metallic line;

depositing a third metallic line on an ILD of a front side of a third wafer;

depositing a fourth metallic line on an ILD of a front side of a fourth wafer;

bonding the third metallic line to the fourth metallic line;

forming a first Si via through an active layer at a back side of the second wafer, the first Si via having an internal end connected to the second metallic line and an external end exposed at the back side of the second wafer;

forming a second Si via through an active layer at a back side of the third wafer, the second Si via having an internal end connected to the third metallic line and an external end exposed at the back side of the third wafer;

increasing areas of the external ends of the first and second Si vias; and

bonding the areas.

10. The method of claim 9, wherein increasing the areas comprises:

forming a trench section in the back side of the second wafer, the trench section filled with a conductive material and connected to the first Si via; and

forming a corresponding trench section in the back side of the third wafer, the corresponding trench section filled with the conductive material and connected to the second Si via.

11. The method of claim 9, wherein increasing the areas comprises:

etching the active layer at the back side of the second wafer at an angle, such that the first Si via is tapered and has a larger cross-sectional area at the external end than at the corresponding internal end.

12. The method of claim 11, further comprising:

forming a third Si via through an active layer at a back side of the fourth wafer, the third Si via connecting to the fourth metallic line of the fourth wafer.

13. The method of claim 12, wherein forming the third Si via comprises:

etching the active layer at the back side of the fourth wafer to form a hole;

depositing oxide on surfaces of the hole;

removing oxide at a bottom surface of the hole using an anisotropic oxide etch;

depositing a barrier layer on oxide on sidewalls of the hole;

depositing a seed layer on the barrier layer; and

filling the hole with a conductive material.

14. The method of claim 13, wherein the barrier layer is composed of a material selected from the group consisting of:

tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W).

15. The method of claim 13, wherein the seed layer comprises a layer of copper atoms deposited by CVD.

16. The method of claim 12, further comprising:

forming a C4 bump on the fourth wafer, the C4 bump physically connecting to the third Si via and electrically connecting to an active layer at a back side of the first wafer.

18. The method of claim 12, wherein forming the first Si via comprises:

etching a part of the active layer at the back side of the first wafer, said etching stopping a tungsten etch stop disposed at an interface between the active layer at the back side of the first wafer and an ILD layer at a front side of the first wafer.

17. A method of metal bonding back sides of two wafers comprising:

forming a first Si via through an active layer at a back side of a first wafer, wherein a first end of the first Si via is exposed;

forming a second Si via through an active layer at a back side of a second wafer, wherein a second end of the second Si via is exposed;

increasing areas of the first end and second end; and

bonding the increased areas.

19. The method of claim 17, wherein increasing the areas comprises:

forming a first trench section in the back side of the first wafer, the first trench section filled with a conductive material and connected to the first Si via; and

forming a second trench section in the back side of the second wafer, the second trench section filled with the conductive material and connected to the second Si via.

20. The method of claim 17, further comprising:

forming a first dummy via in the active layer of the first wafer;

forming a second dummy via in the active layer of the second wafer; and

bonding the first and second dummy vias.