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Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices

  • US 20070111386A1
  • Filed: 11/21/2006
  • Published: 05/17/2007
  • Est. Priority Date: 02/20/2002
  • Status: Abandoned Application
First Claim
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1. A method of metal bonding vertically stacked wafer pairs comprising:

  • forming a first wafer pair, including bonding a metallic line disposed on an ILD on a front side of a first wafer to a corresponding metallic line disposed on an ILD on a front side of a second wafer;

    forming a second wafer pair, including bonding a metallic line disposed on an ILD on a front side of a third wafer to a corresponding metallic line disposed on an ILD on a front side of a fourth wafer;

    providing a first metal bonding area at a back side of the second wafer and a second metal bonding area at a back side of the third wafer, said providing including forming an Si via through an active layer at a back side of the second wafer, wherein a first end of the Si via connects to the metallic line of the second wafer and a second end of the Si via is exposed at the back side of the second wafer;

    increasing the first and second metal bonding areas; and

    bonding the increased first metal bonding area to the increased second metal bonding area.

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