FET Channel Having a Strained Lattice Structure Along Multiple Surfaces

• US 20070111406A1
• Filed: 01/09/2007
• Published: 05/17/2007
• Est. Priority Date: 07/21/2003
• Status: Abandoned Application

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Williams, Richard, Joshi, Rajiv
• Application Number:
  US11/621,290
• Publication Number:
  US 20070111406A1
• Time in Patent Office: Days
• US Class Current: 438/142
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and Si_xGel_1-x, wherein 78<x<92. The channel core 24 has a top surface 26 of width w_c and an upstanding surface 28, 30 of height h_c, preferably oriented 90° to one another. The channel envelope 32 is in contact with the top 26 and upstanding surfaces 28, 30 so that the area of interface is increased as compared to contact only along the top surface 26, improving electrical conductivity and gate 18 control over the channel 16. The height h_c can be tailored to enable a smaller scale FET 10 within a stabilized SRAM. Various methods of making the channel 16 are disclosed, including a mask and etch method, a handle wafer/carrier wafer method, and a shallow trench method. Embodiments and methods for FinFETs with one to four gates are disclosed.

Claims

1-18. -18. (canceled)

19. A Field Effect Transistor disposed on a substrate comprising:

a source;

a drain;

a fin connecting the source to the drain and defining a channel core and a channel envelope;

a gate coupled through a gate dielectric to at least two surfaces of the fin, wherein the channel core defines at least two surfaces extending from the substrate and comprises a first semiconductor material, and the channel envelope is in contact with the at least two surfaces and comprises a second semiconductor material, and wherein at least one of the first or second semiconductor material exhibits one of a stretched and a compressed lattice structure.

20. An integrated circuit comprising at least one field effect transistor according to claim 19.

21. A field effect transistor (FET) comprising:

a source, a drain, a channel, a gate electrode, and a gate dielectric,

wherein the channel comprises a channel core defining a bottom surface and a top surface spaced from the bottom surface by laterally opposed sidewall surfaces disposed between the bottom surface and the top surface,

wherein the channel core comprises a first semiconductor material defining a first lattice structure;

the channel further comprising a channel envelope in contact with at least the top surface of the channel core,

wherein the channel envelope comprises a second semiconductor material defining a second lattice structure that differs from the first lattice structure,

wherein one of the first and second lattice structures is one of stretched and compressed; and

,

wherein the gate electrode is coupled through the gate dielectric to the channel envelope only at a top surface of the channel envelope that is opposed to the top surface of the channel core.

22. The FET of claim 21, wherein the first lattice structure is relaxed relative to the second lattice structure.

23. A field effect transistor (FET) comprising:

a source, a drain, a channel, a gate electrode, and a gate dielectric;

wherein the channel comprises a channel core defining a bottom surface and a top surface spaced from the bottom surface by laterally opposed sidewall surfaces disposed between the bottom surface and the top surface,

wherein the channel core comprises a first semiconductor material defining a first lattice structure;

the channel further comprising a channel envelope in contact with at least the top surface of the channel core,

wherein the channel envelope comprises a second semiconductor material defining a second lattice structure that differs from the first lattice structure; and

,

wherein the gate electrode is coupled through the gate dielectric to the channel envelope only at surfaces of the channel envelope that are opposed to the top and bottom surfaces of the channel core.

24. The FET of claim 23, wherein the first lattice structure is relaxed relative to the second lattice structure.

25. A field effect transistor (FET) comprising:

a source, a drain, a channel, a gate electrode, and a gate dielectric;

wherein the channel comprises a channel core defining a bottom surface and a top surface spaced from the bottom surface by laterally opposed sidewall surfaces disposed between the bottom surface and the top surface,

wherein the channel core comprises a first semiconductor material defining a first lattice structure;

the channel further comprising a channel envelope in contact with at least the top surface and the sidewall surfaces,

wherein the channel envelope comprises a second semiconductor material defining a second lattice structure that differs from the first lattice structure; and

,

wherein the gate electrode is coupled through the gate dielectric to the channel envelope only at surfaces of the channel envelope that are opposed to the top and sidewall surfaces of the channel core.

26. The FET of claim 25, wherein the first lattice structure is relaxed relative to the second lattice structure.

27. A field effect transistor (FET) attached to a substrate comprising:

a source, a drain, a channel, a gate electrode, and a gate dielectric;

wherein the channel comprises a channel core defining a bottom surface and a top surface spaced from the bottom surface by laterally opposed sidewall surfaces disposed between the bottom surface and the top surface,

wherein the channel core comprises a first semiconductor material defining a first lattice structure;

the channel further comprising a channel envelope in contact with at least the top surface,

wherein the channel envelope comprises a second semiconductor material defining a second lattice structure that differs from the first lattice structure; and

,

wherein the gate electrode is coupled through the gate dielectric to the channel envelope at surfaces opposed to the top surface, sidewall surfaces and bottom surface of the channel core.

28. The FET of claim 27, wherein the first lattice structure is relaxed relative to the second lattice structure.

29. A field effect transistor (FET) attached to a substrate comprising:

a source, a drain, a channel, a gate electrode, and a gate dielectric;

wherein the channel comprises a channel core defining a bottom surface and a top surface spaced from the bottom surface by laterally opposed sidewall surfaces disposed between the bottom surface and the top surface,

wherein the channel core comprises a first semiconductor material defining a first lattice structure;

the channel further comprising a channel envelope in contact with at least the top surface,

wherein the channel envelope comprises a second semiconductor material defining a second lattice structure that differs from the first lattice structure; and

,

wherein the gate electrode is coupled through the gate dielectric to the channel envelope at surfaces of the channel envelope that are opposed to the top, sidewall, and bottom surfaces of the channel core.

30. The FET of claim 29, wherein the first lattice structure is relaxed relative to the second lattice structure.

31-35. -35. (canceled)