LOW TEMPERATURE PROCESS AND STRUCTURES FOR POLYCIDE POWER MOSFET WITH ULTRA-SHALLOW SOURCE

• US 20070111446A1
• Filed: 01/12/2007
• Published: 05/17/2007
• Est. Priority Date: 02/09/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Spring, Kyle
• Granted Patent: US 7,473,604 B2
• Time in Patent Office: Days
• US Class Current: 438/259
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench type power semiconductor device includes proud gate electrodes that extend out of the trenches and above the surface of the semiconductor body. These proud gate electrodes allow for making ultra-shallow source regions within the semiconductor body using, for example, a low temperature source drive. In addition, a method for manufacturing the trench type power semiconductor device includes a low temperature process flow once the gate electrodes are formed.

Claims

1. A method for manufacturing a power semiconductor device comprising the steps of:

forming a mask layer over a surface of a semiconductor body of a first conductivity;

patterning said mask with a plurality of openings each opening extending to and exposing the surface of said semiconductor body at the bottom thereof;

defining trenches in said semiconductor body by etching said semiconductor body through said openings, each trench including sidewalls and a bottom and extending to a first depth;

forming an insulation layer on said sidewalls of said trenches;

forming a gate electrode in each of said trenches, each gate electrode including a free end and extending above the surface of said semiconductor body into a respective opening in said mask layer;

removing said mask layer, whereby each gate electrode becomes proud and extends above the surface of said semiconductor body; and

forming a plurality of source regions of said first conductivity in the surface of said semiconductor body such that each of said plurality of source regions extends to a second depth of said semiconductor body, wherein said second depth is approximately equal to or less than a thickness of said insulation layer.

2. The method of claim 1, wherein said device has a gate voltage withstand rating of 12V and said second depth is approximately equal to or less than 300 A.

3. The method of claim 1, wherein all process steps after said removing of said mask layer are less than 900°

C.

4. The method of claim 1, wherein said step of forming a plurality of source regions includes rapid thermal processing with a duration of less than 1 minute.

5. The method of claim 1, further comprising siliciding each gate electrode at its free end prior to removing said mask layer.

6. The method of claim 1, further comprising forming a plurality of contact regions of a second conductivity in the surface of said semiconductor body, each contact region being adjacent to source regions.

7. The method of claim 6, wherein after said steps of forming said plurality of source regions and forming said plurality of contact regions, each of said plurality of source regions and each of said plurality of contact regions have exposed surfaces, said method further comprising the step of siliciding said exposed surfaces of said plurality of source regions and said plurality of contact regions, thereby shorting each contact region to its adjacent source regions.

8. The method of claim 7, further comprising siliciding each gate electrode at its free end prior to removing said mask layer.

9. The method of claim 1, further comprising forming a channel region of a second conductivity in said semiconductor body to a third depth, said first depth of said trenches being greater than said third depth of said channel region.

10. The method of claim 1, wherein each of said plurality of source regions extends from an edge of a trench to a length along the surface of said semiconductor body;

and

wherein said step of forming a plurality of source regions configures said length of each source region to reduce a distance between adjacent trenches, and configures said second depth of each source region to reduce said first depth of each of said plurality of trenches and to thereby reduce a gate charge of said gates.

11. The method of claim 1, further comprising after said step of removing said mask layer the steps of:

forming source implant regions within the surface of said semiconductor body;

forming insulation caps over each of said gate electrodes and covering portions of said source implant regions that are adjacent each trench;

removing portions of said source implant regions not covered by said insulation caps; and

forming contact implant regions of a second conductivity within the surface of said semiconductor body in areas where said source implant regions are removed;

wherein said step of forming a plurality of source regions also forms a plurality of contact regions.

12. The method of claim 11, wherein said step of forming said plurality of source regions and said plurality of contact regions results in each of said plurality of source regions and each of said plurality of contact regions have exposed surfaces, said method further comprising the step of siliciding said exposed surfaces of said plurality of source regions and said plurality of contact regions, thereby shorting each contact region to adjacent source regions.

13. A method for manufacturing a power semiconductor device comprising the steps of:

forming a mask layer over a surface of a semiconductor body of a first conductivity;

patterning said mask with a plurality of openings each opening extending to and exposing the surface of said semiconductor body at the bottom thereof;

defining trenches in said semiconductor body by etching said semiconductor body through said openings, said trenches extending to a first depth;

forming a gate electrode in each of said trenches, each gate electrode including a free end and extending above the surface of said semiconductor body into a respective opening in said mask layer;

removing said mask layer, whereby each gate electrode becomes proud and extends above the surface of said semiconductor body; and

forming a plurality of source regions of said first conductivity in the surface of said semiconductor body;

wherein all process steps after said removing of said mask layer are less than 900°

C.