Semiconductor device with dual gates and method of manufacturing the same

• US 20070111453A1
• Filed: 08/01/2006
• Published: 05/17/2007
• Est. Priority Date: 08/02/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Hag-Ju, Lee, Hye-Lan, Kang, Sang-Bom, Jeon, Taek-Soo, Shin, Yu-Gyun
• Granted Patent: US 7,727,841 B2
• Time in Patent Office: Days
• US Class Current: 438/283
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Abstract

In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.

Claims

1. A semiconductor device with dual gates, comprising:

a semiconductor substrate having a first region on which a MOS transistor of a first conductivity type will be formed and a second region on which a MOS transistor of a second conductivity type will be formed;

a first gate dielectric layer on the semiconductor substrate of the first region;

a first gate electrode on the first gate dielectric layer, the first gate electrode including a lower metallic conductive pattern, an upper metallic conductive pattern, and a first polysilicon layer pattern, which are successively deposited;

a second gate dielectric layer on the semiconductor substrate of the second region;

a second gate electrode on the second gate dielectric layer, the second gate electrode including a second polysilicon layer pattern; and

wherein the lower metallic conductive pattern determines a work function of the first gate electrode.

2. The semiconductor device of claim 1, wherein the lower metallic conductive pattern comprises a metal containing conductive material having a work function suitable to the MOS transistor of the first conductivity type.

3. The semiconductor device of claim 1, wherein the lower metallic conductive pattern comprises any material selected from the group consisting of WN, TaN, TiN, Ni, Pd, Pt, Be, Ir, Te, Re, Ru and Rh.

4. The semiconductor device of claim 1, wherein the upper metallic conductive pattern comprises a metal containing conductive material having an etch selectivity with respect to the lower metallic conductive pattern.

5. The semiconductor device of claim 1, wherein the upper metallic conductive pattern comprises any material selected from the group consisting of TaN, WN, HfN, ZrN, TaSiN, TiSiN, NiSiN, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, Al, Ag, Bi, Cd, Fe, Ta, Ga, Hf, In, Mn, Nb, Y and Zr.

6. The semiconductor device of claim 1, wherein the upper metallic conductive pattern has a thickness of less than about 100 Å

.

7. The semiconductor device of claim 1, wherein the first and second gate dielectric layers comprise a high-k dielectric.

8. The semiconductor device of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type.

9. A semiconductor device with dual gates, comprising:

a semiconductor substrate having a first region on which a MOS transistor of a first conductivity type will be formed and a second region on which a MOS transistor of a second conductivity type will be formed;

a gate dielectric layer on the semiconductor substrate in the first and second regions;

a first gate electrode on the gate dielectric layer of the first region, the first gate electrode including a lower metallic conductive pattern, an upper metallic conductive pattern, and a first polysilicon layer pattern, which are successively deposited;

a second gate electrode on the gate dielectric layer of the second region, the second gate electrode including a second polysilicon layer pattern;

wherein the lower metallic conductive pattern comprises WN; and

wherein the upper metallic conductive pattern comprises TaN.

10. A method of manufacturing a semiconductor device with dual gates, comprising:

providing a semiconductor substrate having a first region on which a MOS transistor of a first conductivity type will be formed and a second region on which a MOS transistor of a second conductivity type will be formed;

forming a dielectric layer, a first metallic conductive layer and a second metallic conductive layer on the first and second regions;

etching the second metallic conductive layer formed on the first metallic conductive layer of the second region, thereby a metal pattern is formed on the first metallic conductive layer of the first region;

etching the first metallic conductive layer formed on the dielectric layer of second region using the metal pattern as an etching mask;

forming a polysilicon layer on the dielectric layer of the second region and the metal pattern of the first region;

forming a first gate electrode by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region, the first gate electrode including a lower metallic conductive pattern, an upper metallic conductive pattern, and a polysilicon pattern; and

forming a second gate electrode by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.

11. The method of claim 10, wherein the first metallic conductive layer comprises a metal containing conductive material having a work function suitable to the MOS transistor of the first conductivity type.

12. The method of claim 10, wherein the first metallic conductive layer comprises any material selected from the group consisting of WN, TaN, TiN, Ni, Pd, Pt, Be, Ir, Te, Re, Ru and Rh.

13. The method of claim 10, wherein the second metallic conductive layer comprises a metal containing conductive material having an etch selectivity with respect to the first metallic conductive layer.

14. The method of claim 10, wherein the second metallic conductive layer comprises any material selected from the group consisting of TaN, WN, HfN, ZrN, TaSiN, TiSiN, NiSiN, Pd, Pt, Be, Ir, Te, Re, Ru, Rh, Al, Ag, Bi, Cd, Fe, Ta, Ga, Hf, In, Mn, Nb, Y and Zr.

15. The method of claim 10, wherein the second metallic conductive layer has a thickness of less than about 100 Å

.

16. The method of claim 10, wherein etching the second metallic conductive layer formed on the first metallic conductive layer of the second region comprises:

forming a photoresist layer pattern on the second metallic conductive layer of the first region;

removing the second metallic conductive layer of the second region using the photoresist layer pattern as an etching mask; and

removing the photoresist layer pattern.

17. The method of claim 10, wherein etching the second metallic conductive layer formed on the first metallic conductive layer of the second region comprises:

forming a hard mask layer on the second metallic conductive layer;

patterning the hard mask layer using a photoresist pattern as an etching mask to form a hard mask layer pattern on the second metallic conductive layer of the first region;

removing the photoresist pattern;

etching the second metallic conductive layer of the second region using the hard mask layer pattern as an etching mask; and

removing the hard mask layer pattern.

18. The method of claim 10, wherein etching the first metallic conductive layer formed on the dielectric layer of second region using the metal pattern as an etching mask is performed by a wet etching process.

19. The method of claim 10, wherein the dielectric layer comprises a high-k dielectric.

20. The method of claim 10, prior to forming the polysilicon layer, further comprising performing a heat treatment process for curing a damage of the dielectric layer caused by etching the first metallic conductive layer of the second region.

21. The method of claim 20, wherein the heat treatment process is performed under an atmosphere including any one selected from the group consisting of N₂, NO, N₂O, O₂, NH₃ and H₂ or a combination thereof.

22. The method of claim 10, wherein the first conductivity type is P-type and the second conductivity type is N-type.

23. The method of claim 10, wherein the first and second gate electrodes are formed substantially simultaneously.