TRENCH INSULATION STRUCTURES AND METHODS

• US 20070111470A1
• Filed: 01/11/2007
• Published: 05/17/2007
• Est. Priority Date: 12/10/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Smythe, John, Budge, William
• Granted Patent: US 7,479,440 B2
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.

Claims

1. A method of forming an isolation structure comprising:

forming a recess within a substrate;

depositing an insulating liner within the recess;

exposing the recess to a plasma process after depositing the insulating liner to form a silicon rich layer at a base of the recess;

depositing a spin-on deposition (SOD) precursor after exposing the recess to the plasma process; and

converting the SOD precursor to an insulating layer, wherein converting the SOD precursor includes expanding the silicon rich layer.

2. The method of claim 1, wherein exposing the recess to the plasma process comprises depositing a silicon layer at the base of the recess.

3. The method of claim 1, wherein depositing an insulating liner comprises depositing a silicon nitride liner layer.

4. The method of claim 3, wherein exposing the recess to the plasma process comprises gettering nitrogen from the silicon nitride liner layer at the base of the recess to form the silicon rich layer.

5. The method of claim 4, wherein expanding the silicon rich layer comprises oxidizing excess silicon of the silicon rich layer at the base of the recess.

6. The method of claim 5, wherein oxidizing thins the silicon nitride liner layer along the base of the recess relative to the silicon nitride liner layer along sidewalls of the recess.

7. The method of claim 1, further comprising forming a thin thermal oxide layer lining the recess before depositing the insulating liner.

8. The method of claim 1, wherein exposing the recess to the plasma process comprises using an anisotropic plasma deposition process.

9. A method of forming a computer memory device comprising:

forming a trench in a substrate;

anisotropically depositing a silicon-based layer along a base of the trench;

depositing an insulator material into the trench after depositing the silicon-based layer; and

converting the silicon-based layer at least partially into silicon oxide during or after depositing the insulator material.

10. The method of claim 9, wherein depositing the insulator material comprises:

depositing a spin-on deposition (SOD) dielectric precursor; and

converting the SOD precursor to a solid insulator.

11. The method of claim 9, wherein anisotropically depositing the silicon-based layer comprises using a plasma deposition process.

12. The method of claim 9, wherein anisotropically depositing the silicon-based layer comprises depositing polysilicon.

13. The method of claim 9, wherein anisotropically depositing the silicon-based layer comprises depositing amorphous silicon.

14. The method of claim 9, wherein anisotropically depositing the silicon-based layer comprises depositing silicon oxide with a silicon percentage greater than a silicon percentage in stoichiometric silicon oxide.

15. The method of claim 9, further comprising forming at least one insulating layer to line the trench before depositing the silicon-based layer.

16. The method of claim 15, wherein forming at least one insulating layer comprises forming a thermal oxide layer lining the trench and a nitride layer over the thermal oxide layer.

17. A method of improving density of a spin-on dielectric comprising:

providing a liner within a recess in a substrate;

depositing silicon on at least part of the liner using a primarily anisotropic plasma deposition process; and

depositing a spin-on deposition (SOD) dielectric precursor within the liner.

18. The method of claim 17, wherein depositing the SOD precursor comprises depositing a polysilazane based SOD material.

19. The method of claim 17, wherein depositing the SOD precursor comprises depositing a silsesquioxane based SOD material.

20. The method of claim 19, wherein depositing the SOD precursor comprises depositing a hydrogen silsesquioxane based SOD material.

21. The method of claim 19, wherein depositing the SOD precursor comprises depositing a methyl silsesquioxane based SOD material.

22. The method of claim 17, wherein providing the liner comprises depositing a silicon nitride layer.

23. The method of claim 17, wherein depositing silicon comprises depositing polysilicon.

24. The method of claim 17, wherein depositing silicon comprises depositing amorphous silicon.