Buffered Thin Module System and Method

• US 20070111606A1
• Filed: 11/28/2006
• Published: 05/17/2007
• Est. Priority Date: 09/03/2004
• Status: Abandoned Application

• Current Assignee: Entorian Technologies
• Original Assignee: Staktek Group LP A Texas Limited Partnership
• Inventors: Goodwin, Paul
• Application Number:
  US11/564,199
• Publication Number:
  US 20070111606A1
• Time in Patent Office: Days
• US Class Current: 439/633
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H05K 1/0203 Cooling of mounted components H05K1/0272 takes precedence
• CPC Class Codes: H05K 1/118 specially for flexible printed circuits, e.g. using folded portions
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 1/189 characterised by the use of a flexible or folded printed circuit H05K3/326 takes precedence
• CPC Class Codes: H05K 2201/056 Folded around rigid support or component
• CPC Class Codes: H05K 2201/1056 Metal over component, i.e. metal plate over component mounted on or embedded in PCB
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2201/2018 Presence of a frame in a printed circuit or printed circuit assembly
• CPC Class Codes: H05K 2203/1572 Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
• CPC Class Codes: H05K 3/0061 onto a metallic substrate, e.g. a heat sink heat sinks for electric apparatus H05K7/20

Abstract

Multiple fully buffered DIMM circuits or instantiations are presented in a single module. In a preferred embodiment, memory integrated circuits (preferably CSPs) and accompanying AMBs are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete FB-DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs.

Claims

1. A circuit module comprising:

a first side and a second side, between which is disposed a substrate having a first perimeter edge and a second perimeter edge;

a plurality of module contacts comprising

a first row of contacts disposed along the first side of the circuit module proximal to the first perimeter edge of the substrate and

a second row of contacts disposed along the second side of the circuit module proximal to the first perimeter edge of the substrate;

a first FB-DIMM circuit comprising a first memory device and a first AMB, the first FB-DIMM circuit connected by first conductive traces to first selected ones of the plurality of module contacts; and

a second FB-DIMM circuit comprising a second memory device and a second AMB the second FB-DIMM circuit connected by second conductive traces to second selected ones of the plurality of module contacts.

2. The circuit module of claim 1 in which the first FB-DIMM circuit is disposed on the first side of the circuit module and the second FB-DIMM circuit is disposed on the second side of the circuit module

3. The circuit module of claim 1 in which the first FB-DIMM circuit is disposed proximal to the second perimeter edge of the substrate and the second FB-DIMM circuit is disposed proximal to the first perimeter edge of the substrate.

4. The circuit module of claim 1 in which the first memory device and the second memory device each comprises plural memory ICs.

5. The circuit module of claim 4 in which the plural memory ICs of the first memory device are arranged in a first field and the plural memory ICs of the second memory device are arranged in a second field.

6. The circuit module of claim 4 in which the plural memory ICs of the first memory device and the first AMB are disposed in a first FB-DIIMM row, and the plural memory ICs of the second memory device and the second AMB are disposed in a second FB-DIMM row.

7. The circuit module of claim 6 in which the first FB-DIMM row is disposed on the first side of the circuit module and the second FB-DIMM row is disposed on the second side of the circuit module.

8. The circuit module of claim 4 in which selected ones of the plural memory ICs of the first memory device are disposed on the first side of the circuit module and the first AMB is disposed on the second side of the circuit module.

9. The circuit module of claim 8 in which selected ones of the plural memory ICs of the second memory device are disposed on the second side of the circuit module and the second AMB is disposed on the first side of the circuit module.

10. The circuit nodule of claim 4 in which the plural memory ICs are deployed in stacks.

11. The circuit module of claim 10 in which the plural memory ICs are CSPs.

12. The circuit module of claim 11 in which each stack of CSPs comprises a mandrel.

13. The circuit module of claim 4 in which first selected ones of the plural memory ICs are disposed on the first side of the circuit module and second selected ones of the plural memory ICs are disposed on the second side of the circuit module, with each of the first selected ones of the plural memory ICs directly opposed to a respective one of the second selected ones of the plural memory ICs disposed on the opposite side of the substrate.

14. The circuit module of claim 4 in which first selected ones of the plural memory ICs are disposed on the first side of the circuit module and second selected ones of the plural memory ICs are disposed on the second side of the circuit module, with the first selected ones of the plural memory ICs offset from the second selected ones of the plural memory ICs disposed on the opposite side of the substrate.

15. A memory module comprising plural FB-DIMM circuits.

16. The memory module of claim 15 in which each of the plural FB-DIMM circuits comprises plural memory CSPs.

17. The memory module of claim 16 in which selected ones of the plural memory CSPs are stacked.

18. The memory module of claim 17 in which selected ones of the stacked plural memory CSPs comprise a mandrel.

19. The memory module of claim 15 in which the first AMB is separated from the second AMB by a single impedance perturbation.

20. A memory module comprising:

a support structure having first and second lateral sides and an edge;

a plurality of module contacts disposed adjacent to the edge of the support structure and supported by the first lateral side of the support structure;

a first FB-DIMM instantiation comprising a first memory device and a first AMB; and

a second FB-DIMM instantiation comprising a second memory device and a second AMB.

21. The memory module of claim 20 in which the first memory device and the second memory device each comprises plural memory ICs.

22. The memory module of claim 21 in which the plural memory ICs of the first memory device and the first AMB are disposed in a first row, and the plural memory ICs of the second memory device and the second AMB are disposed in a second row.

23. The memory module of claim 22 in which the first row is disposed along the first side of the support structure and the second row is disposed along the second side of the support structure.

24. The memory module of claim 21 in which selected ones of the plural memory ICs of the first memory device are disposed along the first side of the support structure and the first AMB is disposed along the second side of the support structure.

25. The memory module of claim 24 in which selected ones of the plural memory ICs of the second memory device are disposed along the second side of the support structure and the second AMB is disposed along the first side of the support structure.

26. The memory module of claim 21 in which the first memory device and the second memory device each comprises stacks of memory ICs.

27. The memory module of claim 26 in which the memory ICs are CSPs.

28. The memory module of claim 27 in which each stack of CSPs comprises a mandrel.

29. A circuit module comprising plural FD-DIMM instantiations.

30. The memory module of claim 29 in which each of the plural FB-DIMM instantiations comprises plural memory CSPs.

31. The memory module of claim 30 in which selected ones of the plural memory CSPs are stacked.

32. The memory module of claim 31 in which selected ones of the stacked plural memory CSPs comprise a mandrel.

33. The memory module of claim 29 in which the first AMB is separated from the second AMB by a single impedance perturbation.

34. A computer comprising:

a motherboard having a socket and

a circuit module connected to the socket, the circuit module comprising plural FB-DIMM instantiations.