High-power amplifier apparatus for TDD wireless communication system

• US 20070111686A1
• Filed: 11/16/2006
• Published: 05/17/2007
• Est. Priority Date: 11/16/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Lee, Jong-Hyun
• Granted Patent: US 7,660,564 B2
• Time in Patent Office: Days
• US Class Current: 455/127.300
• CPC Class Codes: H03F 1/0211 with control of the supply voltage or current
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H04B 1/525 with means for reducing leakage of transmitter signal into the receiver
• CPC Class Codes: H04B 2001/0416 having gain or transmission power control

Abstract

Provided is an HPA apparatus for a TDD wireless communication system. In the HPA apparatus, a power amplifier amplifies the power of an input signal. A gate bias controller turns on/off a gate bias of the power amplifier in accordance with a TDD control signal. A constellation error optimizer circuit removes a current fluctuation and a power noise, which occur when the gate bias controller turns on/off the power amplifier in a TX mode, to stabilize a drain bias thereof.

Claims

1. A high-power amplifier (HPA) apparatus for a Time Division Duplex (TDD) wireless communication system, comprising:

a power amplifier for amplifying the power of an input signal;

a gate bias controller for turning on/off a gate bias of the amplifier in accordance with a TDD control signal; and

a constellation error optimizer circuit being coupled to a drain of the power amplifier for removing a current fluctuation and a power noise.

2. The HPA apparatus of claim 1, wherein the constellation error optimizer comprises:

a bias stabilizer circuit for providing a stable voltage and removing a power noise to stabilize a drain bias of the power amplifier; and

a current control circuit being coupled to the bias stabilizer circuit for removing a current fluctuation that occurs when the gate bias controller turns on the power amplifier.

3. The HPA apparatus of claim 2, wherein the current control circuit comprises:

a direct current/direct current (DC/DC) converter for adjusting a DC level of a received external power;

a filter connected to the converter for performing a filtering operation to reduce a current fluctuation; and

a capacitor connected parallel to the converter and the filter for removing a current spike fluctuation that occurs when the gate bias controller turns on the power amplifier.

4. The HPA apparatus of claim 2, wherein the bias stabilizer circuit comprises:

a regulator for receiving a direct current (DC) power from the current control circuit, and converting the received DC power into a positive voltage;

a first capacitor connected parallel to the regulator for stabilizing the positive voltage output from the regulator; and

a second capacitor connected parallel to the regulator near the power amplifier than the first capacitor for removing a power noise.

5. The HPA apparatus of claim 1, wherein the gate bias controller turns off the gate bias of the power amplifier in a receive (RX) mode.

6. The HPA apparatus of claim 1, wherein the gate bias controller comprises a single-pole single throw (SPST) switch that is installed at a gate bias line of the power amplifier and is switched in accordance with the TDD control signal.

7. The HPA apparatus of claim 1, wherein the TDD control signal is a transistor-transistor logic (TTL) signal or a low-voltage TTL (LVTTL) signal.

8. The HPA apparatus of claim 5, wherein the first capacitor is a tantalum capacitor.

9. The HPA apparatus of claim 5, wherein a capacity of the first capacitor is proportional to a capacity of a transistor in the power amplifier.

10. A power amplifying apparatus in a Time Division Duplex (TDD) wireless communication system, comprising:

a first power amplifier for amplifying the power of an input signal;

a second power amplifier for amplifying the output signal of the first amplifier.

a first gate bias controller for turning on/off a gate bias of the first amplifier in accordance with a TDD control signal;

a second gate bias controller for turning on/off a gate bias of the second amplifier in accordance with the TDD control signal; and

a constellation error optimizer circuit being coupled to a drain of the second power amplifier for removing a current fluctuation and a power noise.

11. The apparatus of claim 10, wherein the constellation error optimizer comprises:

a bias stabilizer circuit for providing a stable voltage and removing a power noise to stabilize a drain bias of the second power amplifier; and

a current control circuit being coupled to the bias stabilizer circuit for removing a current fluctuation that occurs when the gate bias controller turns on the power amplifier.

12. The apparatus of claim 11, wherein the current control circuit comprises:

a direct current/direct current (DC/DC) converter for adjusting a DC level of a received external power;

a filter connected to the converter for performing a filtering operation to reduce a current fluctuation; and

a capacitor connected parallel to the converter and the filter for removing a current spike fluctuation that occurs when the gate bias controller turns on the power amplifier.

13. The apparatus of claim 11, wherein the bias stabilizer circuit comprises:

a regulator for receiving a direct current (DC) power from the current control circuit, and converting the received DC power into a positive voltage;

a first capacitor connected parallel to the regulator for stabilizing the positive voltage output from the regulator; and

a second capacitor connected parallel to the regulator near the power amplifier than the first capacitor for removing a power noise.

14. A power amplifying apparatus in a Time Division Duplex (TDD) wireless communication system, comprising:

a first power amplifier for amplifying the power of an input signal;

a second power amplifier for amplifying the output signal of the first amplifier.

a first gate bias controller for turning on/off a gate bias of the first amplifier in accordance with a TDD control signal;

a second gate bias controller for turning on/off a gate bias of the second amplifier in accordance with the TDD control signal; and

a constellation error optimizer circuit being coupled to a drain of the first power amplifier and a drain of the second power amplifier for removing a current fluctuation and a power noise.

15. The apparatus of claim 14, wherein the constellation error optimizer comprises:

a bias stabilizer circuit for providing a stable voltage and removing a power noise to stabilize a drain bias of first the power amplifier and the second power amplifier; and

a current control circuit being coupled to the bias stabilizer circuit for removing a current fluctuation that occurs when the gate bias controller turns on the first and second power amplifier.

16. The apparatus of claim 15, wherein the current control circuit comprises:

a direct current/direct current (DC/DC) converter for adjusting a DC level of a received external power;

a filter connected to the converter for performing a filtering operation to reduce a current fluctuation; and

a capacitor connected parallel to the converter and the filter for removing a current spike fluctuation that occurs when the gate bias controller turns on the first and the second power amplifier.

17. The apparatus of claim 15, wherein the bias stabilizer circuit comprises:

a regulator for receiving a direct current (DC) power from the current control circuit, and converting the received DC power into a positive voltage;

a first capacitor connected parallel to the regulator for stabilizing the positive voltage output from the regulator; and

a second capacitor connected parallel to the regulator near the power amplifier than the first capacitor for removing a power noise.

18. The apparatus of claim 14, wherein the first and the second gate bias controllers turn off the gate bias of the first and second power amplifiers respectively in a receive (RX) mode.

19. The apparatus of claim 14, wherein the first and second gate bias controllers comprise a single-pole single throw (SPST) switch that is installed at a gate bias line of the first and second power amplifier respectively.

20. The apparatus of claim 14, wherein the TDD control signal is a transistor-transistor logic (TTL) signal or a low-voltage TTL (LVTTL) signal.