Secure booting of an electronic apparatus with SMP architecture
First Claim
1. A method of secure booting of an electronic apparatus that includes plural processors and an external shared memory that are linked by at least one communication bus, each processor having hardware elements and a stack of software elements that can execute on said hardware elements, the method comprising:
- a) securely booting of a first of said processors, up to but not including a software element corresponding to an operating system;
b) protecting, by said first processor, a part of the shared memory, in such a way as to form a secure domain that includes said first processor and of said protected part of the shared memory;
c) booting the operating system of said first processor, including storing data of said operating system in said protected part of the shared memory;
d) securely booting a second of said processors, up to but not including a software element corresponding to an operating system;
then e) authenticating the second processor with the first processor and vice versa, and, in case of successful authentications, f) extending the secure domain to the second processor, wherein said first processor provides to said second processor, a write-access entitlement to said protected part of the shared memory;
then g) booting the operating system of said second processor, including storing data of said operating system of the second processor in said protected part of the shared memory.
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Accused Products
Abstract
A method of secure booting of an SMP architecture apparatus provides for the formation of a secure domain comprising a first processor and a part of a shared memory, before the booting of the operating system of the first processor. The operating system of a second processor is booted only after the reciprocal authentication with the first processor and, in case of authentication, the extension of the secure domain to the second processor.
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Citations
25 Claims
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1. A method of secure booting of an electronic apparatus that includes plural processors and an external shared memory that are linked by at least one communication bus, each processor having hardware elements and a stack of software elements that can execute on said hardware elements, the method comprising:
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a) securely booting of a first of said processors, up to but not including a software element corresponding to an operating system;
b) protecting, by said first processor, a part of the shared memory, in such a way as to form a secure domain that includes said first processor and of said protected part of the shared memory;
c) booting the operating system of said first processor, including storing data of said operating system in said protected part of the shared memory;
d) securely booting a second of said processors, up to but not including a software element corresponding to an operating system;
thene) authenticating the second processor with the first processor and vice versa, and, in case of successful authentications, f) extending the secure domain to the second processor, wherein said first processor provides to said second processor, a write-access entitlement to said protected part of the shared memory;
theng) booting the operating system of said second processor, including storing data of said operating system of the second processor in said protected part of the shared memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An electronic apparatus, comprising:
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a shared memory;
a communication bus; and
a plurality of processors coupled to the shared memory by the communication bus, the plurality of processors including first and second processors, wherein the first processor includes;
means for securely booting the first processor without booting a software element corresponding to an operating system;
means for protecting a part of the shared memory in such a way as to form a secure domain that includes the first processor and the protected part of the shared memory;
means for booting the operating system of the first processor, including storing data of the operating system in the protected part of the shared memory;
means for authenticating the second processor; and
means for extending the secure domain to the second processor if the second processor is successfully authenticated, wherein the first processor provides to the second processor a write-access entitlement to the protected part of the shared memory, wherein the second processor includes;
means for securely booting the second processor without booting a software element corresponding to an operating system of the second processor;
means for authenticating the first processor, wherein the means for extending the secure domain to the second processor operates in response to successful authentication of the first and second processors; and
means for booting the operating system of the second processor, including storing data of said operating system of the second processor in the protected part of the shared memory. - View Dependent Claims (11, 12, 13, 14)
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15. A method of secure booting of an electronic apparatus that includes first and second processors, comprising:
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booting a portion of the second processor that does not include an operating system of the second processor;
authenticating the second processor using the first processor;
authenticating the first processor using the second processor;
if both of the first and second processors are successfully authenticated, then;
providing from the first processor to the second processor access to a protected memory portion of a shared memory; and
booting the operating system of the second processor, including storing data used by the operating system in the protected memory portion. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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Specification