Standby Mode for Power Management

• US 20070113111A1
• Filed: 11/13/2006
• Published: 05/17/2007
• Est. Priority Date: 11/14/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Dahan, Franck, Dubost, Gilles, Seigneret, Franck
• Granted Patent: US 7,809,961 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An apparatus and method for controlling standby mode in an electronic device. In standby mode, power and clock signals are reduced or stopped to conserve power. The apparatus includes an initiator module coupled to a power and clock control module (PCCM). When the initiator module meets conditions for standby mode, the initiator module sends a standby signal to the PCCM and does not interact with other initiator, target, or interconnect modules. When the PCCM communicates a wait signal, the initiator module enters standby mode. When the initiator module detects a wakeup event, the standby signal is deactivated. In this state, the initiator module may process information but may not interact with other modules. When the PCCM deactivates the wait signal and returns power and clock signal to steady state levels, initiator module may resume normal operation.

Claims

1. A method, comprising:

activating a first signal to a control module;

activating a second signal from the control module;

entering a standby mode;

deactivating the first signal to the control module; and

deactivating the second signal from the control module.

2. The method of claim 1, comprising limiting functionality of an initiator module in standby mode.

3. The method of claim 2, comprising reducing power consumed by the initiator module during standby mode.

4. The method of claim 2, comprising stopping power to the initiator module during standby mode.

5. The method of claim 2, comprising controlling at least one clock signal to the initiator module during standby mode.

6. The method of claim 5, comprising reducing the frequency of the at least one clock signal to the initiator module during standby mode.

7. The method of claim 5, comprising stopping the at least one clock signal to the initiator module during standby mode.

8. The method of claim 2, comprising limiting power and at least one clock signal to an interconnect module when the initiator module is in standby mode, said interconnect module capable of transferring information between the initiator module and other modules.

9. The method of claim 2, comprising allowing the initiator module communication with the control module and limiting communication with other modules once the first signal is active.

10. The method of claim 2, comprising allowing the initiator module communication with only the control module once the first signal is active.

11. The method of claim 2, wherein the first signal to the control module is activated when the initiator module is capable of entering standby mode.

12. The method of claim 1, comprising:

deactivating the first signal when a wakeup event to exit standby mode occurs;

deactivating the second signal after deactivating the first signal; and

exiting standby mode.

13. The method of claim 12, wherein the standby mode wakeup event further comprises at least one of the following:

receiving an interrupt signal; and

needing to communicate with an initiator, target, or interconnect module.

14. The method of claim 13, wherein the initiator module includes a DMA controller capable of receiving a DMA request, the wakeup event further comprising receiving a DMA request.

15. The method of claim 12, comprising delaying exit from standby mode for at least one clock cycle.

16. An apparatus, comprising:

a control module;

an initiator module coupled to the control module, wherein the initiator module is capable of transmitting a standby signal to the control module; and

wherein the control module is capable of transmitting a wait signal to the initiator module.

17. The apparatus of claim 16, wherein the initiator module is a processor, graphics accelerator, display controller, audio interface, digital signal processor, microcontroller unit (MCU), direct memory access (DMA) device, video accelerator, or a universal serial bus (USB) device.

18. The apparatus of claim 16, wherein the control module is capable of transmitting the wait signal to the initiator module after the control module receives the standby signal.

19. The apparatus of claim 16, wherein the initiator module is capable of entering a standby mode after the control module activates the wait signal to the initiator module.

20. The apparatus of claim 19, wherein the control module is capable of transmitting a power signal and at least one clock signal to the initiator module.

21. The apparatus of claim 20, wherein the control module is capable of limiting the power and the at least one clock signal to the initiator module in standby mode.

22. The apparatus of claim 19, wherein the standby signal is activated and deactivated synchronously to the at least one clock signal transmitted to the initiator module and the wait signal is activated and deactivated synchronously to the at least one clock signal transmitted to the initiator module.

23. The apparatus of claim 19, wherein the standby signal is capable of deactivating asynchronously to the at least one clock signal transmitted to the initiator module and the wait signal is capable of activating asynchronously to the at least one clock signal transmitted to the initiator module.

24. The apparatus of claim 19, wherein the initiator module exits standby mode after the control module deactivates the wait signal.

25. The apparatus of claim 19, wherein the initiator module is capable of entering a forced standby mode if processing in the initiator module is not enabled and the standby signal is activated.

26. The apparatus of claim 19, wherein the initiator module is capable of entering a no standby mode, the no standby mode further comprising the standby signal not activating.

27. The apparatus of claim 16, further comprising:

a target module coupled to the control module, wherein the control module is capable of transmitting power and at least one clock signal to the target module; and

an interconnect module coupled between the initiator module and the target module, said control module capable of transmitting power and at least one clock signal to the interconnect module.

28. The apparatus of claim 27, wherein the interconnect module is capable of transmitting information between the initiator module and the target module.

29. The apparatus of claim 27, wherein the initiator module is capable of generating read and write requests to the target module.

30. The apparatus of claim 27, wherein the control module is capable of limiting the power and the at least one clock signal to the initiator module, the interconnect module, and the target module when the initiator module is in standby mode.

31. The apparatus of claim 30, wherein the wait signal is deactivated when the power and the at least one clock signal to the initiator module, the interconnect module, and the target module are returned to normal operating levels.

32. An apparatus, comprising:

at least one target module; and

an initiator module coupled to the at least one target module, wherein the initiator module further comprises;

a processing logic unit;

a system interface unit coupled to the processing logic unit and the at least one target module; and

a standby interface unit (SIU) coupled to the system interface unit and the processing logic unit, wherein the SIU is capable of determining if the initiator module may enter and exit a standby mode, a forced standby mode, or a no standby mode.

33. The apparatus of claim 32, comprising a register, wherein the SIU is capable of determining if the initiator module may enter and exit standby mode, forced standby mode, or no standby mode by reading the contents of the register.

34. The apparatus of claim 32, comprising:

an external interface unit coupled to the processing logic unit; and

an external device coupled to the external interface unit, wherein the external device indicates to the SIU that the initiator module exit standby mode.