High-Speed Transceiver Tester Incorporating Jitter Injection

• US 20070113119A1
• Filed: 10/26/2006
• Published: 05/17/2007
• Est. Priority Date: 10/27/2005
• Status: Active Grant

• Current Assignee: DFT Microsystems, Inc.
• Original Assignee: DFT Microsystems, Inc.
• Inventors: Pishdad, Bardia, Hafed, Mohamed, Laberge, Sebastien, Tam, Clarence
• Granted Patent: US 8,327,204 B2
• Time in Patent Office: Days
• US Class Current: 714/700
• CPC Class Codes: G01R 31/31709 Jitter measurements; Jitter generators measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901
• CPC Class Codes: H04B 17/15 Performance testing
• CPC Class Codes: H04B 17/20 of receivers

Abstract

A tester for testing high-speed serial transceiver circuitry. The tester includes a jitter generator that uses a rapidly varying phase-selecting signal to select between two or more differently phased clock signals to generate a phase-modulated signal. The phase-selecting signal is designed to contain low-and high-frequency components. The phase-modulated signal is input into a phase filter to filter unwanted high-frequency components. The filtered output of the phase filter is input into a data-transmit serializer to serialize a low-speed parallel word into a high-speed jittered test pattern for input into the transceiver circuitry.

Claims

1. A high-speed digital tester, comprising:

a jitter generator that includes;

a multiplexer configured to receive a first clock input signal and a second clock input signal phased-shifted relative to said first clock input signal by a delay, said multiplexer having a multiplexer output and a multiplexer select port;

a phase filter operatively connected to said multiplexer output; and

a phase selection signal generator in operative communication with said multiplexer select port and configured to generate a phase-selecting signal for continually selecting between said first clock signal and said second clock signal.

2. The high-speed digital tester according to claim 1, wherein said delay is constant during each of a plurality of high-speed tests.

3. The high-speed digital tester according to claim 2, wherein said delay is programmable so as to allow said delay to be varied among said plurality of tests.

4. The high-speed digital tester according to claim 1, wherein said phase-selecting signal has a low-frequency component and a high-frequency component and said phase filter has a pass band selected to pass said low-frequency component and stop said high-frequency component.

5. The high-speed digital tester according to claim 1, wherein said phase filter comprises a phase-locked loop (PLL).

6. The high-speed digital tester according to claim 1, wherein said phase filter has a filter output and the digital tester further comprises a parallel-data serializer having a serializer select port in operative communication with said filter output.

7. The high-speed digital tester according to claim 6, wherein said data serializer includes a plurality of data input ports and the tester further comprises a deserializer having a plurality of data output ports in communication with corresponding respective ones of said plurality of data input ports of said serializer.

8. The high-speed digital tester according to claim 7, wherein said deserializer is configured to receive a serial data stream having a clock timing and the tester further comprises a clock recovery unit for recovering the clock timing from the serial data stream.

9. The high-speed digital tester according to claim 1, wherein said phase selection signal generator comprises a circular memory.

10. The high-speed digital tester according to claim 9, wherein said circular memory contains multiplexer control data generated by a simulated sigma-delta modulator.

11. The high-speed digital tester according to claim 1, wherein said phase selection signal generator comprises a sigma-delta modulator.

12. The high-speed digital tester according to claim 1, further comprising a coarse delay configured to delay said first clock input signal by said delay so as to create said second clock input signal.

13. The high-speed digital tester according to claim 1, wherein said multiplexer receives at least three differently phased clock input signals.

14. The high-speed digital tester according to claim 13, wherein said phase selection signal generator comprises a multi-bit-width circular memory.

15. The high-speed digital tester according to claim 13, wherein said multiplexer is configured to receive a number N of differently phased clock input signals and the digital tester further comprises N-1 coarse delay elements having differing delays for creating a sequence of said N differently phased clock input signals.

16. A method of generating a high-speed jittered test pattern, comprising:

generating a rapidly varying phase signal containing a low-frequency phase signal and at least one high-frequency component;

filtering said rapidly varying phase signal so as to create a filtered phase signal substantially lacking said at least one high-frequency component; and

serializing parallel data as a function of said filtered phase signal so as to create a high-speed jittered test pattern.

17. The method according to claim 16, wherein the step of generating said rapidly varying phase signal includes alternatingly selecting from among a plurality of differently phased clock signals.

18. The method according to claim 17, wherein the step of alternatingly selecting from among said plurality of differently phased clock signals is performed using a phase selection signal.

19. The method according to claim 18, further comprising a step of generating said phase selection signal.

20. The method according to claim 19, wherein the step of generating said phase selection signal includes triggering a circular memory.

21. The method according to claim 20, wherein the step of generating said phase selection signal includes triggering a multi-bit-width circular memory.

22. The method according to claim 16, wherein the step of generating said rapidly varying phase signal includes selecting between a clock signal and a delayed clock signal in accordance with periodic sigma-delta modulation.

23. The method according to claim 16, wherein the step of filtering said rapidly varying phase signal comprises inputting said rapidly varying phase signal into a phase-locked loop.

24. A method of testing a device under test having a serial receive port and a serial transmit port,

generating a rapidly varying phase signal containing a low-frequency phase signal and at least one high-frequency component comprising:

generating a rapidly varying phase signal containing a low-frequency phase signal and at least one high-frequency component;

filtering said rapidly varying phase signal so as to create a filtered phase signal substantially lacking said at least one high-frequency component;

serializing parallel data on a plurality of data input ports as a function of said filtered phase signal so as to create a serial test pattern;

inputting said serial test pattern into the serial receive port of the device under test;

receiving a serial data signal from the serial transmit port of the device under test;

deserializing said serial data signal into parallel data so as to create a deserialized data signal;

and

reserializing said deserialized data signal for input into the serial receive port of the device under test.

25. The method according to claim 24, wherein the step of generating said rapidly varying phase signal includes alternatingly selecting one clock signal from among a plurality of differently phased clock signals.

26. The method according to claim 24, wherein the step of filtering said rapidly varying phase signal comprises inputting said rapidly varying phase signal into a phase-locked loop.

27. The method according to claim 24, wherein said serial data signal includes clock timing and the method further comprises the step of recovering said clock timing from said serial data signal.

28. A method of testing a device under test having a serial receive port and a serial transmit port, comprising:

enabling the device under test to transmit a serial data signal on its serial transmit port;

receiving said serial data signal from the serial transmit port of the device under test;

deserializing said serial data signal into parallel data;

inputting said parallel data into a plurality of data input ports of a serializer;

generating a rapidly varying phase signal containing a low-frequency phase signal and at least one high-frequency component;

filtering said rapidly varying phase signal so as to create a filtered phase signal substantially lacking said at least one high-frequency component;

serializing data on said plurality of data input ports as a function of said filtered phase signal so as to create a serial test signal;

inputting said serial test signal into the serial receive port of the device under test; and

enabling the device under test to compare the received signal against said serial data signal.