Testing and Recovery in a Multilayer Device

• US 20070113126A1
• Filed: 10/04/2006
• Published: 05/17/2007
• Est. Priority Date: 10/24/2005
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Inapac Technology Incorporated (Rambus Inc.)
• Inventors: Ong, Adrian
• Granted Patent: US 7,779,311 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically connected to the underlying circuit via micro-scale interconnects. The systems are capable of testing the auxiliary circuit and/or interconnects using an interface within the underlying circuit. For example, the auxiliary circuit may be tested although it is mounted such that the interconnects are hidden, i.e., inaccessible for testing purposes after assembly using conventional testing systems and methods. The systems and methods further allow for including excess circuits and/or excess interconnects that can be reconfigured to replace parts of the auxiliary circuit and/or micro-scale interconnects found defective during testing.

Claims

1. A system comprising:

an underlying circuit;

an auxiliary circuit mounted on the underlying circuit;

a plurality of micro-scale interconnects configured to electrically connect the underlying circuit to the auxiliary circuit; and

an interface within the underlying circuit and configured for testing the auxiliary circuit or the plurality of micro-scale interconnects.

2. The system of claim 1, wherein each of the plurality of micro-scale interconnects are 25 microns or less in width.

3. The system of claim 1, wherein the auxiliary circuit includes one or more memory circuits.

4. The system of claim 1, further comprising a plurality of excess interconnects configured for replacing members of the plurality of micro-scale interconnects found to be defective through the testing of the plurality of micro-scale interconnects.

5. The system of claim 4, wherein the interface is further configured to receive programming instructions responsive to test data generated through the testing of the plurality of micro-scale interconnects, and configured for using the plurality of excess interconnects as replacements for defective members of the plurality of micro-scale interconnects.

6. The system of claim 1, further comprising a plurality of excess circuits configured for use as replacements for parts of the auxiliary circuit found to be defective through the testing of the auxiliary circuit.

7. The system of claim 6, wherein the plurality of excess circuits is included in the auxiliary circuit.

8. The system of claim 6, wherein the interface is configured to receive programming instructions responsive to test data generated through the testing of the auxiliary circuit, and configured to use the plurality of excess circuits to replace defective parts of the auxiliary circuit.

9. The system of claim 8, wherein the programming instructions are configured to program a memory controller.

10. The system of claim 8, wherein the test data is generated prior to the mounting of the auxiliary circuit on the underlying circuit, and the programming instructions are received following the mounting of the auxiliary circuit on the underlying circuit.

11. The system of claim 8, further including an automated testing equipment/programmer configured to generate the test data.

12. The system of claim 6, wherein the auxiliary circuit includes one or more memory circuits and the plurality of excess circuits includes memory configurable for replacing defective memory cells in the memory circuits.

13. The system of claim 6, wherein the interface is further configured to convey a signal from an electrical connector to the auxiliary circuit in a test mode, and to convey another signal from the electrical connector elsewhere in a normal operation mode.

14. A method comprising:

mounting an auxiliary circuit on an underlying circuit via a plurality of micro-scale interconnects; and

thereafter using an interface within the underlying circuit to generate first test results data configured to test parts of the auxiliary circuit or parts of the plurality of micro-scale interconnects.

15. The method of claim 14, wherein the first test results data further include an identity of parts of the underlying circuit that include defects.

16. The method of claim 14, further comprising mounting a plurality of excess circuits on the underlying circuit.

17. The method of claim 16, wherein the auxiliary circuit includes one or more memory circuits and the plurality of excess circuits includes memory configurable to replace defective memory cells in the memory circuits.

18. The method of claim 16, further comprising replacing parts of the auxiliary circuit identified as including defects using one or more of the plurality of excess circuits in response to the first test results data.

19. The method of claim 16, wherein the step of mounting the auxiliary circuit is performed contemporaneously with the step of mounting a plurality of excess circuits.

20. The method of claim 14, wherein the step of mounting the auxiliary circuit includes mounting the auxiliary on the underlying circuit via a plurality of excess micro-scale interconnects.

21. The method of claim 20, further comprising using one or more excess interconnects as replacements for parts of the plurality of micro-scale interconnects identified as including defects.

22. The method of claim 21, wherein the step of using the one or more excess interconnects as replacements is performed using the interface within the underlying circuit.

28. A set of integrated circuit systems produced using the method of claim 14 and including excess interconnects or circuits.

23. An integrated circuit system comprising:

an underlying circuit;

an auxiliary circuit mounted on the underlying circuit;

a plurality of excess circuits included in the underlying circuit or the auxiliary circuit, and configured for replacing parts of the auxiliary circuit found to be defective through testing of the auxiliary circuit; and

a plurality of micro-scale interconnects configured to electrically connect the underlying circuit to the auxiliary circuit.

24. The integrated circuit system of claim 23, wherein the plurality of excess circuits is included in the auxiliary circuit.

25. The integrated circuit of claim 23, wherein the auxiliary circuit includes one or more memory circuits and the plurality of excess circuits includes memory configurable for replacing defective memory cells in the memory circuits.

26. An integrated circuit comprising:

an underlying circuit;

an auxiliary circuit mounted on the underlying circuit;

a plurality of micro-scale interconnects configured to electrically connect the underlying circuit to the auxiliary circuit; and

a plurality of excess interconnects configured for replacing parts of the plurality of micro-scale interconnects found to be defective through testing of the plurality of micro-scale interconnects.

27. The integrated circuit of claim 26, wherein each of the plurality of excess interconnects are 25 microns or less in width.