SURROUND GATE ACCESS TRANSISTORS WITH GROWN ULTRA-THIN BODIES
First Claim
1. An access array for memory cells comprising:
- a semiconductive substrate;
a plurality of first conductors formed in a first direction along a surface of the substrate;
a plurality of transistors formed on the surface of the substrate so as to be offset from associated first conductors and at least partially connected to the associated first conductors; and
a plurality of second conductors formed in a second direction and electrically connected with associated transistors such that the transistors can be turned on and off by application of appropriate potentials to the second conductors.
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Accused Products
Abstract
A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.
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Citations
7 Claims
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1. An access array for memory cells comprising:
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a semiconductive substrate;
a plurality of first conductors formed in a first direction along a surface of the substrate;
a plurality of transistors formed on the surface of the substrate so as to be offset from associated first conductors and at least partially connected to the associated first conductors; and
a plurality of second conductors formed in a second direction and electrically connected with associated transistors such that the transistors can be turned on and off by application of appropriate potentials to the second conductors. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification