Switching regulator with hysteretic mode control using zero-ESR output capacitors

• US 20070114983A1
• Filed: 11/21/2005
• Published: 05/24/2007
• Est. Priority Date: 11/21/2005
• Status: Abandoned Application

• Current Assignee: Micrel Incorporated (Microchip Technology Incorporated)
• Original Assignee: Micrel Incorporated (Microchip Technology Incorporated)
• Inventors: Weng, Matthew, Vinn, Charles
• Application Number:
  US11/284,554
• Publication Number:
  US 20070114983A1
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: H01G 4/40 Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H02M 3/1563 without using an external clock H02M3/158 takes precedence

Abstract

A switching regulator integrated circuit for controlling first and second switches in a hysteretic mode using a zero or very low equivalent series resistance (ESR) capacitor includes an integrated circuit package housing a switching regulator semiconductor chip, a first package lead on the integrated circuit package receiving the regulated output voltage and a second package lead to be coupled to a zero or low ESR capacitor of the LC filter. The first package lead may be connected to a first bond pad of the semiconductor chip using a first bond wire. A second bond wire connects the second package lead to the first package lead, or to the first bond pad, or to a second bond pad electrically shorted to the first bond pad. The capacitor is thus electrically coupled to the regulated output voltage and the second bond wire provides series resistance to the capacitor.

Claims

1. A switching regulator integrated circuit for controlling a first switch and a second switch in a hysteretic mode to drive a switch output node for generating a switching output voltage, the switch output node to be coupled to an LC filter circuit to generate a regulated output voltage having a substantially constant magnitude, the switching regulator integrated circuit comprising:

an integrated circuit package housing a switching regulator semiconductor chip comprising control circuitry formed thereon;

a first package lead on the integrated circuit package receiving the regulated output voltage;

a second package lead on the integrated circuit package to be coupled to a capacitor of the LC filter, the capacitor having zero or very low equivalent series resistance (ESR);

a first bond wire connecting the first package lead to a first bond pad on the switching regulator semiconductor chip; and

a second bond wire connecting the second package lead to one of the first package lead, the first bond pad, or a second bond pad electrically shorted to the first bond pad,

wherein the capacitor is coupled to the second package lead to be electrically coupled to the regulated output voltage and the second bond wire provides series resistance to the capacitor.

2. The switching regulator integrated circuit of claim 1, wherein the regulated output voltage is coupled through the first bond pad to control circuitry on the switching regulator semiconductor chip.

3. The switching regulator integrated circuit of claim 1, further comprising a third package lead on the integrated circuit package receiving a feedback voltage, the feedback voltage being indicative of the regulated output voltage, the third package lead being connected to a third bond pad on the switching regulator semiconductor chip through a third bond wire.

4. The switching regulator integrated circuit of claim 3, wherein the feedback voltage comprises a divided down voltage of the regulated output voltage.

5. The switching regulator integrated circuit of claim 1, wherein the capacitor having zero or very low equivalent series resistance comprises a capacitor having an equivalent series resistance of 0.05 ohms or less.

6. The switching regulator integrated circuit of claim 1, wherein when the second bond wire is connected to the first bond pad, the first bond pad comprises an enlarged bond pad for accommodating the first and second bond wires.

7. A switching regulator integrated circuit for controlling a first switch and a second switch in a hysteretic mode to drive a switch output node for generating a switching output voltage, the switch output node to be coupled to an LC filter circuit to generate a regulated output voltage having a substantially constant magnitude, the switching regulator integrated circuit comprising:

an integrated circuit package housing a switching regulator semiconductor chip comprising control circuitry formed thereon;

a first package lead on the integrated circuit package receiving the regulated output voltage;

a second package lead on the integrated circuit package to be coupled to a capacitor of the LC filter, the capacitor having zero or very low equivalent series resistance (ESR); and

a first bond wire connecting the first package lead to the second package lead,

wherein the capacitor is coupled to the second package lead to be electrically coupled to the regulated output voltage and the first bond wire provides series resistance to the capacitor.

8. The switching regulator integrated circuit of claim 7, further comprising a second bond wire connecting the first package lead to a first bond pad on the switching regulator semiconductor chip, wherein the regulated output voltage is coupled through the first bond pad to control circuitry on the switching regulator semiconductor chip.

9. The switching regulator integrated circuit of claim 7, further comprising a third package lead on the integrated circuit package receiving a feedback voltage, the feedback voltage being indicative of the regulated output voltage, the third package lead being connected to a second bond pad on the switching regulator semiconductor chip through a third bond wire.

10. The switching regulator integrated circuit of claim 9, wherein the feedback voltage comprises a divided down voltage of the regulated output voltage.

11. The switching regulator integrated circuit of claim 7, wherein the capacitor having zero or very low equivalent series resistance comprises a capacitor having an equivalent series resistance of 0.05 ohms or less.

12. A method in a switching regulator for controlling a first switch and a second switch in a hysteretic mode to drive a switch output node for generating a switching output voltage, the switch output node to be coupled to an LC filter circuit to generate a regulated output voltage having a substantially constant magnitude, the method comprising:

housing a switching regulator semiconductor chip in an integrated circuit package, the switching regulator semiconductor chip comprising control circuitry formed thereon;

providing a first package lead on the integrated circuit package;

coupling the regulated output voltage to the first package lead;

connecting the first package lead to a first bond pad on the switching regulator semiconductor chip using a first bond wire;

providing a second package lead on the integrated circuit package;

coupling a capacitor of the LC filter to the second package lead, the capacitor having zero or very low equivalent series resistance (ESR); and

connecting the second package lead to one of the first package lead, the first bond pad, or a second bond pad electrically shorted to the first bond pad using a second bond wire, the capacitor thereby being electrically coupled to the regulated output voltage and the second bond wire provides series resistance to the capacitor.

13. The method of claim 12, further comprising:

providing a third package lead on the integrated circuit package;

coupling a feedback voltage to the third package lead, the feedback voltage being indicative of the regulated output voltage; and

connecting the third package lead to a third bond pad on the switching regulator semiconductor chip using a third bond wire.

14. The method of claim 13, wherein the feedback voltage comprises a divided down voltage of the regulated output voltage.

15. The method of claim 12, wherein the capacitor having zero or very low equivalent series resistance comprises a capacitor having an equivalent series resistance of 0.05 ohms or less.

16. The method of claim 12, wherein when the second bond wire is connected to the first bond pad, the first bond pad comprises an enlarged bond pad for accommodating the first and second bond wires.

17. A method in a switching regulator for controlling a first switch and a second switch in a hysteretic mode to drive a switch output node for generating a switching output voltage, the switch output node to be coupled to an LC filter circuit to generate a regulated output voltage having a substantially constant magnitude, the method comprising:

housing a switching regulator semiconductor chip in an integrated circuit package, the switching regulator semiconductor chip comprising control circuitry formed thereon;

providing a first package lead on the integrated circuit package;

coupling the regulated output voltage to the first package lead;

providing a second package lead on the integrated circuit package;

coupling a capacitor of the LC filter to the second package lead, the capacitor having zero or very low equivalent series resistance (ESR); and

connecting the first package lead to the second package lead using a first bond wire, the capacitor thereby being electrically coupled to the regulated output voltage and the first bond wire provides series resistance to the capacitor.

18. The method of claim 17, further comprising connecting the first package lead to a first bond pad on the switching regulator semiconductor chip using a second bond wire, wherein the regulated output voltage is coupled through the first bond pad to control circuitry on the switching regulator semiconductor chip.

19. The method of claim 17, further comprising:

providing a third package lead on the integrated circuit package;

coupling a feedback voltage to the third package lead, the feedback voltage being indicative of the regulated output voltage; and

connecting the third package lead to a second bond pad on the switching regulator semiconductor chip using a third bond wire.

20. The method of claim 19, wherein the feedback voltage comprises a divided down voltage of the regulated output voltage.

21. The method of claim 17, wherein the capacitor having zero or very low equivalent series resistance comprises a capacitor having an equivalent series resistance of 0.05 ohms or less.