STRUCTURE AND METHOD FOR MONITORING STRESS-INDUCED DEGRADATION OF CONDUCTIVE INTERCONNECTS
First Claim
1. A method of testing an ability of a microelectronic element having conductive interconnects to withstand thermal stress, comprising:
- providing an interconnect test structure within said microelectronic element, said interconnect test structure including;
i) a conductive metallic plate having an upper surface, a lower surface opposite said upper surface, and a plurality of peripheral edges extending between said upper surface and said lower surface, said upper surface defining a horizontally extending plane, said metallic plate having a width in a widthwise direction, a length in a lengthwise direction, and a thickness in a direction of a height of said upper surface from said lower surface, ii) a lower via consisting essentially of at least one of conductive or semiconductive material having a top end in conductive communication with said metallic plate and a bottom end vertically displaced from said top end, and iii) an upper metallic via in at least substantial vertical alignment with said lower conductive via, said upper metallic via having a bottom end in conductive communication with said metallic plate and a top end vertically displaced from said bottom end, said upper metallic via having a width at least about ten times smaller than a larger one of said length of said metallic plate and said width of said metallic plate;
maintaining said microelectronic element at an elevated temperature for a predetermined period of time;
taking a first measurement of at least one electrical characteristic of said interconnect test structure prior to an end of said predetermined period of time;
taking a second measurement of said at least one electrical characteristic of said interconnect test structure at a time not prior to an end of said predetermined period of time; and
comparing a difference between said first and second measurements to at least one failure criterion to determine whether said microelectronic element passes or fails.
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Abstract
A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
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Citations
30 Claims
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1. A method of testing an ability of a microelectronic element having conductive interconnects to withstand thermal stress, comprising:
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providing an interconnect test structure within said microelectronic element, said interconnect test structure including;
i) a conductive metallic plate having an upper surface, a lower surface opposite said upper surface, and a plurality of peripheral edges extending between said upper surface and said lower surface, said upper surface defining a horizontally extending plane, said metallic plate having a width in a widthwise direction, a length in a lengthwise direction, and a thickness in a direction of a height of said upper surface from said lower surface, ii) a lower via consisting essentially of at least one of conductive or semiconductive material having a top end in conductive communication with said metallic plate and a bottom end vertically displaced from said top end, and iii) an upper metallic via in at least substantial vertical alignment with said lower conductive via, said upper metallic via having a bottom end in conductive communication with said metallic plate and a top end vertically displaced from said bottom end, said upper metallic via having a width at least about ten times smaller than a larger one of said length of said metallic plate and said width of said metallic plate;
maintaining said microelectronic element at an elevated temperature for a predetermined period of time;
taking a first measurement of at least one electrical characteristic of said interconnect test structure prior to an end of said predetermined period of time;
taking a second measurement of said at least one electrical characteristic of said interconnect test structure at a time not prior to an end of said predetermined period of time; and
comparing a difference between said first and second measurements to at least one failure criterion to determine whether said microelectronic element passes or fails. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A microelectronic element, comprising:
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a plurality of conductive interconnects, at least some of said conductive interconnects including;
a metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between said upper surface and said lower surface, said upper surface defining a horizontally extending plane, said metallic plate having a width in a widthwise direction, a length in a lengthwise direction, and a thickness in a direction of a height of said upper surface from said lower surface;
a metallic connecting line having an upper surface at least substantially level with said upper surface of said metallic plate, an inner end connected to said metallic plate at one of said peripheral edges, and an outer end horizontally displaced from said one peripheral edge, said metallic connecting line having a width much smaller than said width of said one peripheral edge and a length greater than said width of said one peripheral edge, an upper metallic via having a bottom end in contact with said metallic connecting line at a location horizontally displaced from said one peripheral edge by at least about 3 microns (μ
m). - View Dependent Claims (14, 15, 16, 17, 19)
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- 18. The conductive interconnect structure as claimed in claimed 13, wherein said metallic plate has a plurality of dielectric filled openings extending vertically between said upper surface and said lower surface.
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21. A structure representative of a conductive interconnect in a microelectronic element for purposes of modeling stress-induced degradation, comprising:
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a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between said upper surface and said lower surface, said upper surface defining a horizontally extending plane, said metallic plate having a width in a widthwise direction, a length in a lengthwise direction, and a thickness in a direction of a height of said upper surface from said lower surface;
a lower via consisting essentially of at least one of conductive or semiconductive material having a top end in conductive communication with said metallic plate and a bottom end vertically displaced from said top end;
a lower element consisting essentially of at least one of conductive or semiconductive material in contact with said bottom end of said lower via;
an upper metallic via in at least substantial vertical alignment with said lower conductive via, said upper metallic via having a bottom end in conductive communication with said metallic plate and a top end vertically displaced from said bottom end, said upper metallic via having a width at least about ten times than said length and at least about ten times smaller than said width; and
an upper metallic line element in contact with said top end of said upper metallic via. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification