Circuit configuration having a feedback, fully-differential operational amplifier

• US 20070115050A1
• Filed: 11/15/2006
• Published: 05/24/2007
• Est. Priority Date: 11/21/2005
• Status: Active Grant

• Current Assignee: National Semiconductor Germany AG (Texas Instruments, Inc.)
• Original Assignee: Xignal Technologies AG (Texas Instruments, Inc.)
• Inventors: Blon, Thomas
• Granted Patent: US 7,414,467 B2
• Time in Patent Office: Days
• US Class Current: 330/69
• CPC Class Codes: H03F 2203/45511 the feedback circuit [FBC] comprising one or more transistor stages, e.g. cascaded stages of the dif amp, and being coupled between the loading circuit [LC] and the input circuit [IC]
• CPC Class Codes: H03F 2203/45526 the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
• CPC Class Codes: H03F 3/45941 Controlling the input circuit of the differential amplifier

Abstract

The present invention relates to a circuit configuration having a feedback operational amplifier (AMP), which is implemented as fully differential, for amplifying an input signal differentially input to the circuit configuration and for outputting the amplified input signal as a differential output signal. In order to increase the freedom in setting the input common mode voltage, according to the present invention, a combination made of a coupling resistor (R1b) and a level shifter (I1b, Nsfb) connecting the positive amplifier output (y1) to the inverting amplifier input (x2) and a combination made of a coupling resistor (R1a) and a level shifter (I1a, Nsfa) connecting the negative amplifier output (y2) to the noninverting amplifier input (x1) are provided.

Claims

1. A circuit configuration having a circuit input (inp, inn) for an input signal to be amplified and a circuit output (outn, outp) for outputting the amplified input signal as an output signal,

the circuit configuration having a operational amplifier (AMP) implemented as fully-differential, having a noninverting amplifier input (x1), an inverting amplifier input (x2), a positive amplifier output (y1) and a negative amplifier output (y2),

the circuit input (inp, inn) being connected via coupling paths to the amplifier inputs (x1, x2) and the amplifier outputs (y1, y2) being connected via decoupling. paths to the circuit output (outp, outn) and via feedback paths to the amplifier inputs (x2, x1),

characterized by a combination made of a coupling resistor (R1b) and a level shifter (I1b, Nsfb) connecting the positive amplifier output (y1) to the inverting amplifier input (x2) and a combination made of a coupling resistor (R1a) and a level shifter (I1a, Nsfa) connecting the negative amplifier output (y2) to the noninverting amplifier input (x1).

2. The circuit configuration according to claim 1, wherein at least a part of the coupling paths are formed by impedances having a capacitive component.

3. The circuit configuration according to claim 1, wherein at least a part of the feedback paths are formed by impedances having a capacitive component.

4. The circuit configuration according to claim 1, wherein the coupling resistors (R1a, R1b) are each implemented as an ohmic resistor having a resistance value of more than 1 MΩ

.

5. The circuit configuration according to claim 1, wherein the two level shifters (I1a, Nsfa, I1b, Nsfb) each comprise a transistor (Nsfa, Nsfb) powered using a constant current source (I1a, I1b).

6. The circuit configuration according to claim 5, wherein the transistor (Nsfa, Nsfb) is an FET.

7. The circuit configuration according to claim 1, wherein the two level shifters (I1a, Nsfa, I1b, Nsfb) are constructed identically.

8. The circuit configuration according to claim 1, wherein the operational amplifier (AMP) has a setting input for setting the output common mode voltage (Vcm).

9. The circuit configuration according to claim 1, wherein the operational amplifier (AMP) is connected to a first supply potential (GND) and a second supply potential (vdd) for its supply and the output common mode voltage (Vcm) is set as a. predetermined fraction of the supply voltage (vdd-GND).

10. The circuit configuration according to claim 9, wherein the fraction is in the range from 40% to 60%.

11. The circuit configuration according to claim 1, wherein the operational amplifier (AMP) is connected to a first supply potential (GND) and a second supply potential (vdd) for its supply and the output common mode voltage (Vcm) is set as the supply voltage (vdd-GND) reduced by a predetermined reduction voltage.

12. The circuit configuration according to claim 11, wherein the reduction voltage is in the range from 40 to 60% of a rated supply voltage (vdd-GND) of the operational amplifier (AMP).

13. The circuit configuration according to claim 1, wherein the coupling paths for changing a circuit amplification each comprise impedances (C3a, C3b) which are each connectable and disconnectable via a transistor (Nsa, Nsb).