Self-referenced differential decoding of analog baseband signals

• US 20070115160A1
• Filed: 11/16/2006
• Published: 05/24/2007
• Est. Priority Date: 11/18/2005
• Status: Abandoned Application

• Current Assignee: ZeroG Wireless, Inc. (Microchip Technology Incorporated)
• Original Assignee: ZeroG Wireless, Inc. (Microchip Technology Incorporated)
• Inventors: Lee, Thomas, Xu, Junfeng, Kleveland, Bendik, Wong, Dickson
• Application Number:
  US11/600,945
• Publication Number:
  US 20070115160A1
• Time in Patent Office: Days
• US Class Current: 341/144
• CPC Class Codes: H04L 27/2331 wherein the received signal is demodulated using one or more delayed versions of itself

Abstract

Apparatus and methods of differentially decoding analog baseband signals are described. In one aspect, a wireless communication apparatus includes a baseband filtering stage and a differential decoder stage. The baseband filtering stage receives a DPSK analog baseband signal differentially encoded with phase shift differences in successive symbol periods. The baseband filtering stage selectively passes frequencies in the DPSK analog baseband signal within a passband frequency range to produce a filtered analog signal. The differential decoder includes a delay circuit and a combiner circuit. The delay circuit produces from the filtered analog signal a reference signal that preserves values of a feature of the filtered analog signal for one symbol period. The combiner circuit combines values of a feature of the filtered analog signal during a current symbol period with values of the reference signal to produce a resultant signal representing a differential decoding of the DPSK analog baseband signal.

Claims

1. A wireless communication apparatus, comprising:

a baseband filtering stage operable to receive a differential phase shift keyed (DPSK) analog baseband signal differentially encoded with phase shift differences in successive symbol periods, the baseband filtering stage being operable to selectively pass frequencies in the DPSK analog baseband signal within a passband frequency range to produce a filtered analog signal; and

a differential decoder comprising a delay circuit and a combiner circuit, wherein the delay circuit produces from the filtered analog signal a reference signal that preserves values of a feature of the filtered analog signal for one symbol period, and the combiner circuit combines values of a feature of the filtered analog signal during a current symbol period with values of the reference signal to produce a resultant signal representing a differential decoding of the DPSK analog baseband signal.

2. The apparatus of claim 1, wherein the delay circuit comprises:

a delay line that delays the filtered analog signal by one symbol period to produce the reference signal; and

the combiner circuit comprises a mixer that mixes the filtered analog signal with the reference signal to produce the resultant signal.

3. The apparatus of claim 2, wherein the differential decoder comprises a one-bit analog-to-digital converter that converts the resultant signal to a differentially decoded digital signal.

4. The apparatus of claim 2, wherein the delay line comprises an analog delay line circuit that delays the filtered analog signal by one symbol period.

5. The apparatus of claim 2, wherein the delay line comprises a digitizer that produces a digitized signal from the filtered analog signal, and a digital delay line circuit that delays the digitized signal by one symbol period to produce the reference signal.

6. The apparatus of claim 5, wherein the digitizer comprises a zero-crossing threshold detector that produces the digitized signal with values representing zero-crossings in the filtered analog signal.

7. The apparatus of claim 5, wherein the digitizer comprises a level sensing hysteresis circuit that produces the digitized signal from the filtered analog signal.

8. The apparatus of claim 2, wherein the delay line comprises a sample-and-hold circuit that is clocked by multiple non-overlapping clock signals each having a respective period equal to the sample period.

9. The apparatus of claim 1, comprising:

a first mixer that mixes an input signal with an in-phase local oscillator (LO) signal to produce the DPSK analog baseband signal;

a second mixer that mixes the input signal with an in-quadrature version of the LO signal to produce a quadrature-phase DPSK analog baseband signal;

an in-phase signal path that includes the baseband filtering stage, the differential decoder, and has an in-phase output that produces the output signal representing the differential decoding of the DPSK analog signal;

a quadrature-phase signal path that includes a second baseband filtering stage equivalent to the first baseband filtering stage, a second differential decoder equivalent to the first differential decoder, and has a quadrature-phase output that produces a second output signal representing a differential decoding of the quadrature-phase DPSK analog baseband signal.

10. The apparatus of claim 9, further comprising:

an adder having a first input coupled to the in-phase output, a second input coupled to the quadrature-phase output, and an adder output that outputs the resultant signal; and

a one-bit analog-to-digital coupled to the adder output and operable to convert the resultant signal into digital data representing a digital decoding of the DPSK analog baseband signal.

11. The apparatus of claim 9, further comprising a third mixer operable to downconvert an RF signal to produce an intermediate frequency (IF) signal;

and an IF filter coupled to the third mixer and operable to filter the IF signal to produce the input signal.

12. The apparatus of claim 1, wherein the baseband filtering stage comprises a high pass filtering coupling capacitor coupled to an input of a low pass filter circuit.

13. The apparatus of claim 1, wherein:

the delay circuit produces the reference signal with a respective high logic value for one symbol period in response to each detection of a rising edge of the filtered analog signal, and the delay circuit additionally produces a second reference signal with a respective high logic value for one symbol period in response to each detection of a falling edge of the filtered analog signal; and

the combiner circuit produces the resultant signal with values corresponding to a logical NOR of the values of the first and second signals.

14. The apparatus of claim 1, wherein the delay circuit comprises a first one-shot circuit that is triggered on rising edges of the filtered analog signal and a second one-shot circuit that is triggered on falling edges of the filtered analog signal, and the combiner circuit comprises a NOR logic gate having inputs coupled to the first and second one-shot circuits and an output that produces the resultant signal.

15. The apparatus of claim 14, wherein each of the first and second one-shot circuits comprises:

an edge detector that extracts an edge feature of the filtered analog signal;

a set-reset latch having a set input coupled to the edge detector, a reset input, and a latch output; and

a delay line that has an input coupled to the latch output, and an output that is coupled to the reset input of the latch and one of the inputs of the NOR logic gate.

16. The apparatus of claim 14, wherein the baseband filtering stage comprises a low pass filter circuit having differential inputs coupled to receive the DPSK analog signal as a differential pair of signals and differential outputs each coupled through a respective high pass filtering coupling capacitor to an input of a respective one of the first and second one-shot circuits.

17. A wireless communication method, comprising:

receiving a differential phase shift keyed (DPSK) analog baseband signal differentially encoded with phase shift differences in successive symbol periods;

bandpass filtering the DPSK analog baseband signal by selectively passing frequencies in the DPSK analog baseband signal within a passband frequency range to produce a filtered analog signal;

producing from the filtered analog signal a reference signal that preserves values of a feature of the filtered analog signal for one symbol period; and

combining values of a feature of the filtered analog signal during a current symbol period with values of the reference signal to produce a resultant signal representing a differential decoding of the DPSK analog baseband signal.

18. The method of claim 17, wherein the producing comprises delaying the filtered analog signal by one symbol period to produce the reference signal, and the combining comprises mixing the filtered analog signal with the reference signal to produce the resultant signal.

19. The method of claim 17, wherein:

the producing comprises producing the reference signal with a respective high logic value for one symbol period in response to each detection of a rising edge of the filtered analog signal, and producing a second reference signal with a respective high logic value for one symbol period in response to each detection of a falling edge of the filtered analog signal; and

the combining comprises producing the resultant signal with values corresponding to a logical NOR of the values of the first and second reference signals.

20. A wireless communication apparatus, comprising:

means for receiving a differential phase shift keyed (DPSK) analog baseband signal differentially encoded with phase shift differences in successive symbol periods;

means for bandpass filtering the DPSK analog baseband signal by selectively passing frequencies in the DPSK analog baseband signal within a passband frequency range to produce a filtered analog signal;

means for producing from the filtered analog signal a reference signal that preserves values of a feature of the filtered analog signal for one symbol period; and

means for combining values of a feature of the filtered analog signal during a current symbol period with values of the reference signal to produce a resultant signal representing a differential decoding of the DPSK analog baseband signal.