Radio receiver, system on a chip integrated circuit and methods for use therewith

• US 20070115161A1
• Filed: 11/22/2005
• Published: 05/24/2007
• Est. Priority Date: 11/22/2005
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: May, Michael, Lowe, Erich
• Granted Patent: US 7,391,347 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 2215/065 by changing the frequency of clock or reference frequency
• CPC Class Codes: H04H 40/18 Arrangements characterised by circuits or components specially adapted for receiving

Abstract

A system on a chip integrated circuit includes a first digital module a second digital module such that the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal. A digital clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and generates a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period.

Claims

1. A radio receiver comprising:

an analog front end for receiving a received radio signal containing a selected one of the plurality of channel signals, and for converting the selected one of the plurality of channel signals into a digital signal;

a digital clock generator, for generating a base clock signal at a base clock frequency that varies based on the selected one of the plurality of channel signals and for generating a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period; and

a digital section, operably coupled to the analog front end and the digital clock generator, for converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, the digital section having a first digital module that operates based on the first digital clock signal and a second digital module that operates based on the second digital clock signal.

2. The radio receiver of claim 1 wherein the digital clock generator includes a stall cycle module for producing a first stall signal and a second stall signal in response to a first value of the control signal, wherein the digital clock generator produces the first digital clock signal by selectively inserting at least one stall cycle in response to the first stall signal and produces the second digital clock signal by selectively inserting at least one stall cycle in response to the second stall signal.

3. The radio receiver of claim 2 wherein the digital clock generator further includes:

a first delay module for producing the first digital clock signal by inserting a first delay in a first preliminary clock signal having a duration of one stall cycle, and

a second delay module for producing the second digital clock signal by inserting a second delay in a second preliminary clock signal having a duration of one stall cycle.

4. The radio receiver of claim 3 wherein the digital clock generator further includes:

a preliminary clock cycle generator for producing the first preliminary clock signal and the second preliminary clock signal.

5. The radio receiver of claim 2 wherein the first stall signal is asserted at least one time when the second stall signal is deasserted and wherein the second stall signal is asserted at least one time when the first stall signal is deasserted.

6. The radio receiver of claim 1 wherein the plurality of first digital clock cycles are not equal to the plurality of second digital clock cycles over the predetermined period.

7. The radio receiver of claim 1 wherein the digital clock generator generates a base clock signals at a base digital clock frequency that varies based on the selected one of the plurality of channel signals and wherein the plurality of first digital clock cycles and the plurality of second digital clock cycles are substantially constant over the predetermined period.

8. The radio receiver of claim 3 wherein the base clock frequency is less than a carrier frequency of the selected one of the plurality of channel signals and wherein the base digital clock frequency, and integer multiples of the digital clock frequency are not substantially equal to the Carrier frequency of the selected one of the plurality of channel signals.

9. The radio received of claim 1 wherein the predetermined period is one of:

a sample period, a decimation period, and a computational period.

10. The radio receiver of claim 1 wherein the digital clock generator generates at least one of the plurality of first digital clock cycles in synchronism with at least one of the plurality of second digital clock cycles over the predetermined period.

11. The radio receiver of claim 1 wherein the received radio signal is one of:

a broadcast frequency modulated radio signal, a broadcast amplitude modulated radio signal, a broadcast satellite radio signal, IBOC digital radio signal, Bluetooth radio signal and a broadcast cable signal.

12. A system on a chip integrated circuit comprising:

a first digital module;

a second digital module; and

a digital clock generator, operably coupled to the first digital module and the second digital module, for generating a base clock signal at a base clock frequency that varies based on a control signal and for generating a first digital clock signal having a substantially constant number of first digital luck cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period;

wherein the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal.

13. The system on a chip integrated circuit of claim 12 wherein the digital clock generator includes a stall cycle module for producing a first stall signal and a second stall signal in response to a first value of the control signal, wherein the digital clock generator produces the first digital clock signal by selectively inserting at least one stall cycle in response to the first stall signal and produces the second digital clock signal by selectively inserting at least one stall cycle in response to the second stall signal.

14. The system on a chip integrated circuit of claim 13 wherein the digital clock generator further includes:

a first delay module for producing the first digital clock signal by inserting a first delay in a first preliminary clock signal having a duration of one stall cycle; and

a second delay module for producing the second digital clock signal by inserting a second delay in a second preliminary clock signal having a duration of one stall cycle.

15. The system on a chip integrated circuit of claim 13 wherein the digital clock generator further includes:

a preliminary clock cycle generator for producing the first preliminary clock signal and the second preliminary clock signal.

16. The system on a chip integrated circuit of claim 13 wherein the first stall signal is asserted at least one time when the second stall signal is deasserted and wherein the second stall signal is asserted at least one time when the first stall signal is deasserted.

17. The system on a chip integrated circuit of claim 12 wherein the plurality of first digital clock cycles arc not equal to the plurality of second digital clock cycles over the predetermined period.

18. The system on a chip integrated circuit of claim 12 wherein the predetermined period is one of:

a sample period, a decimation period, and a computational period.

19. Tho system on a chip integrated circuit of claim 12 wherein the digital clock generator generates at least one of the plurality of first digital clock cycles in synchronism with at least one of the plurality of second digital clock cycles over the predetermined period.

20. The system on a chip integrated circuit of claim 12 wherein the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period.

21. A method comprising:

generating a base clock signal at a base clock frequency that varies based on a control signal;

producing a first stall signal and a second stall signal in response to a first value of the control signal;

generating a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period by selectively inserting at least one stall cycle in response to the first stall signal;

generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period by selectively inserting at least one stall cycle in response to the second stall signal.

23. The method of claim 21 wherein the first stall signal is asserted at least one time when the second stall signal is deasserted and wherein the second stall signal is asserted at least one time when the first stall signal is deasserted.

24. The method of claim 21 wherein the plurality of first digital clock cycles are not equal to the plurality of second digital clock cycles over the predetermined period.

25. The method of claim 21 wherein the predetermined period is one of:

a sample period, a decimation period, and a computational period of an integrated circuit.

26. The method of claim 21 wherein at least one of the plurality of first digital clock cycles is in synchronism with at least one of the plurality of second digital clock cycles over the predetermined period.

22. (canceled)

27. An integrated circuit comprising:

a first digital module;

a second digital module; and

a digital clock generator, operably coupled to the first digital module and the second digital module, for generating a base clock signal at a base clock frequency that varies based on a control signal and for generating a first digital clock signal having a number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a number of second digital clock cycles over the predetermined period, wherein the plurality of first digital clock cycles and the plurality of second digital clock cycles are distributed substantially uniformly over the predetermined period;

wherein the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal.

28. The integrated circuit of claim 27 wherein the digital clock generator includes a stall cycle module for producing a first stall signal and a second stall signal in response to a first value of the control signal, wherein the digital clock generator produces the first digital clock signal by selectively inserting at least one stall cycle in response to the first stall signal and produces the second digital clock signal by selectively inserting at least one stall cycle in response to the second stall signal.

29. The integrated circuit of claim 28 wherein the digital clock generator further includes:

a first delay module for producing the first digital clock signal by inserting a first delay in a first preliminary clock signal having a duration of one stall cycle; and

a second delay module for producing the second digital clock signal by inserting a second delay in a second preliminary clock signal having a duration of one stall cycle.

30. That integrated circuit of claim 28 wherein the digital clock generator further includes:

a preliminary clock cycle generator for producing the first preliminary clock signal and the second preliminary clock signal.

31. The integrated circuit of claim 28 wherein the first stall signal is asserted at least one time when the second stall signal is deasserted and wherein the second stall signal is asserted at least one time when the first stall signal is deasserted.

32. The integrated circuit of claim 27 wherein the plurality of first digital clock cycles are not equal to the plurality of second digital clock cycles over the predetermined period.

33. The integrated circuit of claim 27 wherein the predetermined period is one of:

a sample period, a decimation period, and a computational period.

34. The integrated circuit of claim 27 wherein the digital clock generator generates at least one of the plurality of first digital clock cycles in synchronism with at least one of the plurality of second digital clock cycles over the predetermined period.

35. The integrated circuit of claim 27 wherein the second digital module generates an output during the predetermined period tat is based on an output of the first digital module generated during a prior predetermined period.