METHOD AND STRUCTURE FOR CHARGE DISSIPATION IN INTEGRATED CIRCUITS

• US 20070115606A1
• Filed: 11/21/2005
• Published: 05/24/2007
• Est. Priority Date: 11/21/2005
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Preston, Joan, Runyon, Stephen, DeVries, Kenneth, Greco, Nancy
• Granted Patent: US 7,408,206 B2
• Time in Patent Office: Days
• US Class Current: 361/220
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.

Claims

1. An integrated circuit chip, comprising:

an silicon on insulator substrate comprising a bulk silicon substrate, a buried oxide layer on a top surface of said bulk silicon substrate, and a silicon layer on a top surface of said buried oxide layer, said buried oxide layer electrically isolating said silicon layer from said bulk silicon substrate;

a region of shallow trench isolation formed in said silicon layer and extending from said top surface of said buried oxide layer to a top surface of said silicon layer;

a charge dissipation guard ring comprising a continuous polysilicon ring disposed adjacent to sides of said integrated circuit chip and at least a continuous band of a metal contact ring aligned over and in direct physical and electrical contact with a corresponding continuous band of a top surface of said polysilicon ring, of said metal contact ring in said polysilicon ring extending from a top surface of said region of shallow trench isolation, through said shallow trench isolation and through said buried oxide layer in direct physical and electrical contact with said bulk silicon substrate, said polysilicon ring electrically isolated from said silicon layer by said region of shallow trench isolation; and

one or more charge dissipation pedestals, each charge dissipation pedestal of said one or more charge dissipation pedestals comprising a stack of wire segments from a lowermost to a higher most wire segment of each wiring level of said integrated circuit chip, a lowermost wire segment of said stack of wire segments in direct physical and electrical contact with said metal contact ring, each wire segment of said stack of wire segments in direct physical and electrical contact with a lower and a higher wire segment.

2. The integrated circuit chip of claim 1, wherein said continuous metal contact ring comprises a lower continuous ring and a separate upper continuous ring, a continuous band of a top surface of said lower continuous ring in direct physical and electrical contact with a continuous band of a bottom surface of said upper continuous ring.

3. The integrated circuit chip of claim 1, further including:

a functional circuit region containing an integrated circuit, said functional circuit region disposed within and spaced at least a first predetermined distance from said guard ring and spaced at least a second predetermined distance from each of said one or more charge dissipation pedestals.

4. The integrated circuit chip of claim 3, wherein said first and second predetermined distances are a same distance.

5. The integrated circuit chip of claim 3, wherein said integrated circuit includes a ground distribution grid electrically coupled to said silicon layer and physically and electrically connected to said uppermost wire segment of at least one of said one or more charge dissipation pedestals.

6. The integrated circuit chip of claim 1, further including:

a functional circuit region containing an integrated circuit, either said guard ring and at least one of said one or more charge dissipation pedestals disposed within said functional circuit region or at least one of said one or more charge dissipation pedestals disposed within said functional circuit region.

8. The integrated circuit chip of claim 1, wherein said one or more of said one or more charge dissipation pedestals are disposed over one or more different corners of said guard ring, over one or more sides of said guard ring or both over one or more different corners of and one or more sides of said guard ring.

9. The integrated circuit chip of claim 1, further including a continuous crack stop disposed between said sides of said integrated circuit chip and said charge dissipation guard ring and charge dissipation pedestals.

7. The integrated circuit chip of claim 7, wherein said integrated circuit includes a ground distribution grid electrically coupled to said silicon layer and physically and electrically connected to said uppermost wire segment of at least one of said one or more charge dissipation pedestals.

10. An integrated circuit chip, comprising;

a silicon on insulator substrate comprising a bulk silicon substrate, a buried oxide layer on a top surface of said bulk silicon substrate, and a silicon layer on a top surface of said buried oxide layer, said buried oxide layer electrically isolating said silicon layer from said bulk silicon substrate;

a region of shallow trench isolation formed in said silicon layer and extending from said top surface of said buried oxide layer to a top surface of said silicon layer; and

one or more charge dissipation pedestals, each charge dissipation pedestal of said one or more charge dissipation pedestals comprising;

a polysilicon, tungsten or other electrically conductive material filled trench disposed proximate to a side or a corner of said integrated circuit chip and one or more metal contact studs, each aligned over and in direct physical and electrical contact with a top surface of said filled trench, said filled trench extending from a top surface of said region of shallow trench isolation, through said region of shallow trench isolation and through said buried oxide layer in direct physical and electrical contact with said bulk silicon substrate, said filled trench electrically isolated from said silicon layer by said region of shallow trench isolation; and

a stack of wire segments from a lowermost to a higher most wire segment of each wiring level of said integrated circuit chip, a lowermost wire segment of said stack of wire segments in direct physical and electrical contact with each of said one or more metal contact studs, each wire segment of said stack of wire segments in direct physical and electrical contact with a lower and a higher wire segment.

11. The integrated circuit chip of claim 10, wherein said each of said one or more metal contact studs comprises a lower contact stud or wire segment and a separate upper contact stud, a top surface of said lower stud contact or wire segment in direct physical and electrical contact with a bottom surface of said upper contact stud.

12. The integrated circuit chip of claim 10,

wherein said charge dissipation pedestals are all located adjacent to sides of said integrated circuit chip;

and

further including a functional circuit region containing an integrated circuit, said functional circuit region disposed within said integrated circuit chip, said functional circuit region spaced at least a predetermined distance from each of said one or more charge dissipation pedestals.

13. The integrated circuit chip of claim 12, wherein said integrated circuit includes a ground distribution grid electrically coupled to said silicon layer and physically and electrically connected to said uppermost wire segment of at least one of said one or more charge dissipation pedestals.

14. The integrated circuit chip of claim 10, further including a continuous crack stop disposed between said sides of said integrated circuit chip and said charge dissipation pedestals.

15. The integrated circuit chip of claim 10, further including:

a functional circuit region containing an integrated circuit, said functional circuit region disposed within said integrated circuit chip, one or more of said one or more charge dissipation pedestals disposed within said functional circuit region.

16. The integrated circuit chip of claim 15, wherein said integrated circuit includes a ground distribution grid electrically coupled to said silicon layer and physically and electrically connected to said uppermost wire segment of at least one of said one or more charge dissipation pedestals.

17. A method of forming a charge dissipation structure in an integrated circuit, comprising:

providing a silicon on insulator substrate comprising a bulk silicon substrate, a buried oxide layer on a top surface of said bulk silicon substrate, and a silicon layer on a top surface of said buried oxide layer, said buried oxide layer electrically isolating said silicon layer from said bulk silicon substrate;

forming a region of shallow trench isolation formed in said silicon layer and extending from said top surface of said buried oxide layer to a top surface of said silicon layer;

forming a charge dissipation guard ring comprising a continuous polysilicon ring disposed adjacent to sides of said integrated circuit chip and at least a continuous band of a metal contact ring aligned over and in direct physical and electrical contact with a corresponding continuous band of a top surface of said polysilicon ring, of said metal contact ring in said polysilicon ring extending from a top surface of said region of shallow trench isolation, through said shallow trench isolation and through said buried oxide layer in direct physical and electrical contact with said bulk silicon substrate, said polysilicon ring electrically isolated from said silicon layer by said region of shallow trench isolation; and

forming one or more charge dissipation pedestals, each charge dissipation pedestal of said one or more charge dissipation pedestals comprising a stack of wire segments from a lowermost to a higher most wire segment of each wiring level of said integrated circuit chip, a lowermost wire segment of said stack of wire segments in direct physical and electrical contact with said metal contact ring, each wire segment of said stack of wire segments in direct physical and electrical contact with a lower and a higher wire segment.

18. The method of claim 17, wherein said continuous metal contact ring comprises a lower continuous ring and a separate upper continuous ring, a continuous band of a top surface of said lower continuous ring in direct physical and electrical contact with a continuous band of a bottom surface of said upper continuous ring.

19. The method of claim 17, further including forming an integrated circuit within a functional circuit region of said integrated circuit chip, said functional circuit region disposed within and spaced at least a first predetermined distance from said guard ring and spaced at least a second predetermined distance from each of said one or more charge dissipation pedestals.

20. The method of claim 19, wherein said first and second predetermined distances are a same distance.

21. The method of claim 19, wherein said integrated circuit includes a ground distribution grid and further including electrically coupling said ground distribution grid to said silicon layer and physically and electrically connecting said ground distribution grid to said uppermost wire segment of at least one of said one or more charge dissipation pedestals.

22. The method of claim 17, further including:

forming an integrated circuit in a functional circuit region of said integrated circuit chip, either said guard ring and at least one of said one or more charge dissipation pedestals disposed within said functional circuit region or at least one of said one or more charge dissipation pedestals disposed within said functional circuit region.

23. The method of claim 22, wherein said integrated circuit includes a ground distribution grid electrically coupled to said silicon layer and physically and electrically connected to said uppermost wire segment of at least one of said one or more charge dissipation pedestals.

24. The method of claim 17, wherein said one or more of said one or more charge dissipation pedestals are disposed over one or more different corners of said guard ring, over one or more sides of said guard ring or both over one or more different corners of and one or more sides of said guard ring.

25. The method of claim 17, further including forming a continuous crack stop disposed between said sides of said integrated circuit chip and said charge dissipation guard ring and charge dissipation pedestals.

31. The method of claim 23,

wherein said charge dissipation pedestals are all located adjacent to sides of said integrated circuit chip;

and

further including forming a functional circuit region containing a functional integrated circuit, said functional circuit region disposed within said integrated circuit chip, one or more of said one or more charge dissipation pedestals disposed within said functional circuit region.

32. The method of claim 31, wherein said integrated circuit includes a ground distribution grid electrically coupled to said silicon layer and physically and electrically connected to said uppermost wire segment of at least one of said one or more charge dissipation pedestals.

26. A method of forming a charge dissipation structure in an integrated circuit, comprising:

providing a silicon on insulator substrate comprising a bulk silicon substrate, a buried oxide layer on a top surface of said bulk silicon substrate, and a silicon layer on a top surface of said buried oxide layer, said buried oxide layer electrically isolating said silicon layer from said bulk silicon substrate;

forming a region of shallow trench isolation formed in said silicon layer and extending from said top surface of said buried oxide layer to a top surface of said silicon layer; and

forming one or more charge dissipation pedestals, each charge dissipation pedestal of said one or more charge dissipation pedestals comprising;

a polysilicon, tungsten or other electrically conductive material filled trench disposed proximate to a side or a corner of said integrated circuit chip and one or more metal contact studs, each aligned over and in direct physical and electrical contact with a top surface of said filled trench, said filled trench extending from a top surface of said region of shallow trench isolation, through said shallow trench isolation and through said buried oxide layer in direct physical and electrical contact with said bulk silicon substrate, said filled trench electrically isolated from said silicon layer by said region of shallow trench isolation; and

a stack of wire segments from a lowermost to a higher most wire segment of each wiring level of said integrated circuit chip, a lowermost wire segment of said stack of wire segments in direct physical and electrical contact with each of said one or more metal contact studs, each wire segment of said stack of wire segments in direct physical and electrical contact with a lower and a higher wire segment.

27. The method of claim 26, wherein said each of said one or more metal contact studs comprises a lower contact stud or wire segment and a separate upper contact stud, a top surface of said lower stud contact or wire segment in direct physical and electrical contact with a bottom surface of said upper contact stud.

28. The method of claim 26,

wherein said charge dissipation pedestals are all located adjacent to sides of said integrated circuit chip;

and

further including forming a functional circuit region containing an integrated circuit, said functional circuit region disposed within said integrated circuit chip, said functional circuit region spaced at least a predetermined distance from each of said one or more charge dissipation pedestals.

29. The method of claim 28, wherein said integrated circuit includes a ground distribution grid electrically coupled to said silicon layer and physically and electrically connected to said uppermost wire segment of at least one of said one or more charge dissipation pedestals.

30. The method of claim 26, further including:

forming a continuous crack stop disposed between said sides of said integrated circuit chip and said charge dissipation pedestals.

33. A method of designing an integrated circuit chip, comprising:

generating a functional chip dataset, said functional chip dataset including an integrated circuit design and either (a) a charge dissipation guard ring design and a charge dissipation pedestal design or (b) only said charge dissipation pedestal design;

generating a kerf design dataset; and

merging said functional chip design dataset and said kerf design dataset to generate an integrated circuit chip design dataset.

34. The method of claim 33, wherein:

if said charge dissipation guard ring design exists, said charge dissipation guard ring design comprises a charge dissipation guard ring comprising a either (c) a continuous polysilicon ring disposed adjacent to sides of said integrated circuit chip and at least a continuous band of a metal contact ring aligned over and in direct physical and electrical contact with a corresponding continuous band of a top surface of said polysilicon ring, said polysilicon ring extending from a top surface of said region of shallow trench isolation, through said shallow trench isolation and through said buried oxide layer in direct physical and electrical contact with said bulk silicon substrate, said polysilicon ring electrically isolated from said silicon layer by said region of shallow trench isolation or (d) a continuous metal contact ring extending from said top surface of said region of shallow trench isolation, through said shallow trench isolation and through said buried oxide layer, said continuous metal contact ring in direct physical and electrical contact with said bulk silicon substrate, said metal ring electrically isolated from said silicon layer by said region of shallow trench isolation; and

said charge dissipation pedestal design, comprises a stack of wire segments from a lowermost to a higher most wire segment of each wiring level of said integrated circuit chip, a lowermost wire segment of said stack of wire segments in direct physical and electrical contact with said metal contact ring, each wire segment of said stack of wire segments in direct physical and electrical contact with a lower and a higher wire segment.

35. The method of claim 33, further including generating a mask dataset from said integrated circuit chip design dataset.

36. A computer program product comprising a computer useable medium including a computer readable program, wherein the computer readable program when executed on a computer causes the computer to:

generate a functional chip dataset, said functional chip dataset including an integrated circuit design and either (a) a charge dissipation guard ring design and a charge dissipation pedestal design or (b) only said charge dissipation pedestal design;

generate a kerf design dataset; and

merge said functional chip design dataset and said kerf design dataset to generate an integrated circuit chip design dataset.

37. The computer program product of claim 36, wherein:

if said charge dissipation guard ring design exists, said charge dissipation guard ring design comprises either (c) a continuous polysilicon ring disposed adjacent to sides of said integrated circuit chip and at least a continuous band of a metal contact ring aligned over and in direct physical and electrical contact with a corresponding continuous band of a top surface of said polysilicon ring, said polysilicon ring extending from a top surface of said region of shallow trench isolation, through said shallow trench isolation and through said buried oxide layer in direct physical and electrical contact with said bulk silicon substrate, said polysilicon ring electrically isolated from said silicon layer by said region of shallow trench isolation or (d) a continuous metal contact ring extending from said top surface of said region of shallow trench isolation, through said shallow trench isolation and through said buried oxide layer, said continuous metal contact ring in direct physical and electrical contact with said bulk silicon substrate, said metal ring electrically isolated from said silicon layer by said region of shallow trench isolation; and

said charge dissipation pedestal design, comprises a stack of wire segments from a lowermost to a higher most wire segment of each wiring level of said integrated circuit chip, a lowermost wire segment of said stack of wire segments in direct physical and electrical contact with said metal contact ring, each wire segment of said stack of wire segments in direct physical and electrical contact with a lower and a higher wire segment.

38. The computer program product of claim 36, wherein the method further includes generating a mask dataset from said integrated circuit chip design dataset.