Method, system and circuit for programing a non-volatile memory array

• US 20070115726A1
• Filed: 10/17/2006
• Published: 05/24/2007
• Est. Priority Date: 10/29/2002
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Cohen, Guy, Polansky, Yan
• Granted Patent: US 7,675,782 B2
• Time in Patent Office: Days
• US Class Current: 365/185.190
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3468 Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

The present invention is a multi-phase method, circuit and system for programming non-volatile memory (“NVM”) cells in an NVM array. The present invention may include a controller to determine when, during a first programming phase, one or more NVM cells of a first set of cells reaches or exceeds a first intermediate voltage, and to cause a charge pump circuit to apply to a terminal of the one or more cells in the first set second phase programming pulses to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.

Claims

1. A method of programming an array of non-volatile memory (“

NVM”

) cells, said method comprising;

substantially concurrently applying programming pulses to a first set and a second set of NVM cells, wherein the first set of NVM cells is intended to be programmed to a threshold voltage different from that of the second set.

2. The method according to claim 1, further comprising upon one or more NVM cells of the first or second sets of cells reaching or exceeding an intermediate threshold voltage level associated with the given set, applying to a terminal of one or more cells in the given set second phase programming pulses adapted to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.

3. The method according to claim 2, wherein applying first phase programming pulses comprises applying to a terminal an NVM cell incrementally increasing programming pulses in concert with pulses of substantially fixed voltage applied to the gate of the NVM cell.

4. The method according to claim 2, wherein applying second phase programming pulses comprises applying to a terminal of the NVM cell programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage.

5. The method according to the claim 3, wherein applying to a terminals of the one or more cells of the first set second phase programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage is repeated until one or more of the cells of the first set reaches a first target threshold voltage level.

6. The method according to claim 1, further comprising substantially concurrently applying programming pulses to a third set of NVM cells, wherein the third set of NVM cells is intended to be programmed to a threshold voltage different from that of the first and second sets.

7. A System for programming an array of non-volatile memory (“

NVM”

) cells, said system comprising;

a controller adapted to cause a charge pump circuit to substantially concurrently apply programming pulses to a first set and a second set of NVM cells, wherein the first set of NVM cells is intended to be programmed to a threshold voltage different from the that of the second set.

8. The system according to claim 7, wherein said controller is adapted to determine when one or more NVM cells of the first or second sets of cells reaches or exceeds an intermediate threshold voltage level associated with the given set and to cause said charge pump circuit to apply to a terminal of one or more cells in the given set second phase programming pulses adapted to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.

9. The system according to claim 8, wherein said controller is adapted to cause said charge pump circuit to initially apply to a terminal of one or more NVM cells of the first and second sets of NVM cells first phase programming pulses having incrementally increasing voltage levels in concert with pulses of substantially fixed voltage applied to a gate of the one or more NVM cells.

10. The system according to claim 9, wherein said controller is adapted to cause said charge pump circuit to apply second phase programming pulses by applying to a terminal of the NVM cell programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage.

11. The system according to the claim 10, wherein said controller is adapted to cause said charge pump to apply to a terminals of the one or more cells of the first set second phase programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage is repeated until one or more of the cells of the first set reaches a first target threshold voltage level.

12. The system according to claim 7, wherein said controller is further adapted to cause a charge pump circuit to substantially concurrently apply programming pulses to a third set of NVM cells, wherein the third set of NVM cells is intended to be programmed to a threshold voltage different from that of the first and second sets.

13. A non-volatile memory (“

NVM”

) device comprising;

a controller adapted to cause a charge pump circuit to substantially concurrently apply programming pulses to a first set and a second set of NVM cells, wherein the first set of NVM cells is intended to be programmed to a threshold voltage different from the that of the second set.

14. The device according to claim 13, wherein said controller is adapted to determine when one or more NVM cells of the first or second sets of cells reaches or exceeds an intermediate threshold voltage level associated with the given set and to cause said charge pump circuit to apply to a terminal of one or more cells in the given set second phase programming pulses adapted to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.

15. The device according to claim 14, wherein said controller is adapted to cause said charge pump circuit to initially apply to a terminal of one or more NVM cells of the first and second sets of NVM cells first phase programming pulses having incrementally increasing voltage levels in concert with pulses of substantially fixed voltage applied to a gate of the one or more NVM cells.

16. The device according to claim 15, wherein said controller is adapted to cause said charge pump circuit to apply second phase programming pulses by applying to a terminal of the NVM cell programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage.

17. The device according to the claim 16, wherein said controller is adapted to cause said charge pump to apply to a terminals of the one or more cells of the first set second phase programming pulses of substantially fixed voltage in concert with gate pulses of incrementally increasing voltage is repeated until one or more of the cells of the first set reaches a first target threshold voltage level.

18. The device according to claim 17, wherein said controller is further adapted to cause a charge pump circuit to substantially concurrently apply programming pulses to a third set of NVM cells, wherein the third set of NVM cells is intended to be programmed to a threshold voltage different from that of the first and second sets.

19. A multi-phase method of programming an array of non-volatile memory (“

NVM”

) cells, said method comprising;

Applying to a first set of NVM cells first phase programming pulses; and

upon one or more NVM cells of the first set of cells reaching or exceeding a first intermediate threshold voltage level, applying to a terminal of one or more cells in the first set of cells second phase programming pulses adapted to induce deterministically lower programming rate for all cells in first set.

20. A System for programming an array of non-volatile memory (“

NVM”

) cells, said system comprising;

a controller adapted to cause a charge circuit to produce first phase programming pulses and to determine when one or more NVM cell of a first set of cells receiving the first phase programming pulses reaches or exceeds a first intermediate voltage, and to then cause said charge circuit to apply to a terminal of the one or more cells in the first set second phase programming pulses adapted to induce a deterministically reduced programming rate.