Method, system and circuit for programing a non-volatile memory array
First Claim
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1. A method of programming an array of non-volatile memory (“
- NVM”
) cells, said method comprising;
substantially concurrently applying programming pulses to a first set and a second set of NVM cells, wherein the first set of NVM cells is intended to be programmed to a threshold voltage different from that of the second set.
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Abstract
The present invention is a multi-phase method, circuit and system for programming non-volatile memory (“NVM”) cells in an NVM array. The present invention may include a controller to determine when, during a first programming phase, one or more NVM cells of a first set of cells reaches or exceeds a first intermediate voltage, and to cause a charge pump circuit to apply to a terminal of the one or more cells in the first set second phase programming pulses to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.
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Citations
20 Claims
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1. A method of programming an array of non-volatile memory (“
- NVM”
) cells, said method comprising;
substantially concurrently applying programming pulses to a first set and a second set of NVM cells, wherein the first set of NVM cells is intended to be programmed to a threshold voltage different from that of the second set. - View Dependent Claims (2, 3, 4, 5, 6)
- NVM”
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7. A System for programming an array of non-volatile memory (“
- NVM”
) cells, said system comprising;
a controller adapted to cause a charge pump circuit to substantially concurrently apply programming pulses to a first set and a second set of NVM cells, wherein the first set of NVM cells is intended to be programmed to a threshold voltage different from the that of the second set. - View Dependent Claims (8, 9, 10, 11, 12)
- NVM”
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13. A non-volatile memory (“
- NVM”
) device comprising;
a controller adapted to cause a charge pump circuit to substantially concurrently apply programming pulses to a first set and a second set of NVM cells, wherein the first set of NVM cells is intended to be programmed to a threshold voltage different from the that of the second set. - View Dependent Claims (14, 15, 16, 17, 18)
- NVM”
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19. A multi-phase method of programming an array of non-volatile memory (“
- NVM”
) cells, said method comprising;
Applying to a first set of NVM cells first phase programming pulses; and
upon one or more NVM cells of the first set of cells reaching or exceeding a first intermediate threshold voltage level, applying to a terminal of one or more cells in the first set of cells second phase programming pulses adapted to induce deterministically lower programming rate for all cells in first set.
- NVM”
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20. A System for programming an array of non-volatile memory (“
- NVM”
) cells, said system comprising;
a controller adapted to cause a charge circuit to produce first phase programming pulses and to determine when one or more NVM cell of a first set of cells receiving the first phase programming pulses reaches or exceeds a first intermediate voltage, and to then cause said charge circuit to apply to a terminal of the one or more cells in the first set second phase programming pulses adapted to induce a deterministically reduced programming rate.
- NVM”
Specification