Radio receiver, system on a chip integrated circuit and methods for use therewith
First Claim
1. A radio receiver comprising:
- an analog front end for receiving a received radio signal containing a selected one of the plurality of channel signals, and for converting the selected one of the plurality of channel signals into a digital signal;
a digital section, operably coupled to the analog front end and the digital clock generator, for converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, the digital section having a first digital module and a second digital module; and
a digital clock generator, operably coupled to the first digital module and the second digital module, for generating a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period, wherein the plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period;
wherein the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period.
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Abstract
A system on a chip integrated circuit includes a first digital module and a second digital module such that the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period. A digital clock generator generates a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period. The plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period;
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Citations
28 Claims
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1. A radio receiver comprising:
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an analog front end for receiving a received radio signal containing a selected one of the plurality of channel signals, and for converting the selected one of the plurality of channel signals into a digital signal;
a digital section, operably coupled to the analog front end and the digital clock generator, for converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, the digital section having a first digital module and a second digital module; and
a digital clock generator, operably coupled to the first digital module and the second digital module, for generating a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period, wherein the plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period;
wherein the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit (IC) comprising:
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a first digital module;
a second digital module; and
a digital clock generator, operably coupled to the first digital module and the second digital module, for generating a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period, wherein the plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period;
wherein the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method comprising:
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generating a base clock signal having a plurality of first digital clock cycles over a predetermined period to clock a first digital submodule;
generating a second digital clock signal having a plurality of second digital clock cycles over the predetermined period to clock a second digital submodule, wherein the plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period, and wherein the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period. - View Dependent Claims (18, 19, 20, 21, 22)
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23. An integrated circuit (IC) comprising:
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a first digital module;
a second digital module; and
a digital clock generator, operably coupled to the first digital module and the second digital module, for generating a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period, wherein the plurality of first digital clock cycles and the plurality of second digital clock cycles are distributed substantially uniformly over the predetermined period;
wherein the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period. - View Dependent Claims (24, 25, 26, 27, 28)
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Specification