Radio receiver, system on a chip integrated circuit and methods for use therewith

• US 20070116148A1
• Filed: 11/22/2005
• Published: 05/24/2007
• Est. Priority Date: 11/22/2005
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Sigmatel LLC (NXP Semiconductors NV)
• Inventors: May, Michael, Lowe, Erich
• Granted Patent: US 7,656,968 B2
• Time in Patent Office: Days
• US Class Current: 375/316
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 2215/065 by changing the frequency of clock or reference frequency

Abstract

A system on a chip integrated circuit includes an analog front end for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and for converting a selected one of the plurality of channel signals into a digital signal. A digital clock generator generates a digital clock signal at a digital clock frequency that varies based on the selected one of the plurality of channel signals. The digital clock frequency, and integer multiples of the digital clock frequency, are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A digital section converts the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, based on the digital clock signal.

Claims

1. A system on a chip integrated circuit comprising:

an analog front end for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and for converting a selected one of the plurality of channel signals into a digital signal;

a digital clock generator, for generating a digital clock signal at a digital clock frequency that varies based on the selected one of the plurality of channel signals;

a digital section, operably coupled to the analog front end, for converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, based on the digital clock signal;

wherein the digital clock frequency, and integer multiples of the digital clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals.

2. The system on a chip integrated circuit of claim 1 further comprising;

a channel selector, for producing a control signal that corresponds to the selected one of the plurality of channels;

a local oscillator, operably coupled to the analog front end and a reference oscillation, for generating a local oscillation signal based on the control signal;

wherein the digital clock generator includes a divider for dividing the local oscillation signal to produce the digital clock signal.

3. The system on a chip integrated circuit of claim 2 wherein the divider divides by an integer.

4. The system on a chip integrated circuit of claim 3 wherein the integer is equal to six.

5. The system on a chip integrated circuit of claim 2 wherein the divider includes a fractional divider.

6. The system on a chip integrated circuit of claim 1 wherein the digital clock frequency is substantially equal to two-thirds of the carrier frequency of the selected one of the plurality of channel signals.

7. The system on a chip integrated circuit of claim 1 wherein the digital clock frequency is less than the carrier frequency of the selected one of the plurality of channel signals.

8. The system on a chip integrated circuit of claim 1 wherein the received radio signal is one of:

a broadcast frequency modulated radio signal, a broadcast amplitude modulated radio signal, a broadcast satellite radio signal, and a broadcast cable signal.

9. The system on a chip integrated circuit of claim 1 wherein the analog front end includes an in-phase signal path and a quadrature-phase signal path.

22. The system on a chip integrated circuit of claim 2 wherein the divider includes a fractional divider.

10. A method comprising:

receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies;

converting a selected one of the plurality of channel signals into a digital signal;

generating a digital clock signal at a digital clock frequency that varies based on the selected one of the plurality of channel signals;

converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, based on the digital clock signal;

wherein the digital clock frequency, and integer multiples of the digital clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals.

11. The method of claim 10 further comprising;

producing a control signal that corresponds to the selected one of the plurality of channels;

generating a local oscillation signal based on the control signal;

wherein the step of receiving includes mixing the received signal by the local oscillation signal and wherein the step of generating the digital clock signal includes dividing the local oscillation signal to produce the digital clock signal.

12. The method of claim 11 wherein the step of dividing includes dividing by an integer.

13. The method of claim 12 wherein the integer is equal to 6.

14. The method of claim 10 wherein the digital clock frequency is substantially equal to two-thirds of the carrier frequency of the selected one of the plurality of channel signals.

15. The method of claim 10 wherein the digital clock frequency is less than the carrier frequency of the selected one of the plurality of channel signals.

16. The method of claim 10 wherein the received radio signal is one of:

a broadcast frequency modulated radio signal, a broadcast amplitude modulated radio signal, a broadcast satellite radio signal, and a broadcast cable signal.

17. The method of claim 10 wherein the step of receiving includes processing the received radio signal along an in-phase signal path and a quadrature-phase signal path.

18. A radio receiver comprising:

a channel selector, for producing a control signal that corresponds to a selected one of the plurality of channels in a received radio signal having a corresponding carrier frequency;

a local oscillator, operably coupled to the analog front end and a reference oscillation, for generating a local oscillation signal based on the control signal;

a analog front end, operably coupled to the local oscillation signal, for receiving the received radio signal, and for converting the selected one of the plurality of channel signals into a digital signal, wherein the analog front end includes an in-phase signal path and a quadrature-phase signal path;

a digital clock generator, for generating a digital clock signal at a digital clock frequency that varies based on the selected one of the plurality of channel signals;

a digital section, operably coupled to the analog front end, for converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, based on the digital clock signal;

wherein the digital clock frequency is less than the carrier frequency of the selected one of the plurality of channel signals and wherein the digital clock frequency, and integer multiples of the digital clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals.

19. The radio receiver of claim 18 wherein the digital clock generator includes a divider for dividing the local oscillation signal to produce the digital clock signal.

20. The radio receiver of claim 19 wherein the divider divides by an integer.

21. The radio receiver of claim 20 wherein the integer is equal to 6.

23. The radio receiver of claim 18 wherein the digital clock frequency is substantially equal to two-thirds of the carrier frequency of the selected one of the plurality of channel signals.

24. The radio receiver of claim 18 wherein the received radio signal is one of:

a broadcast frequency modulated radio signal, a broadcast amplitude modulated radio signal, a broadcast satellite radio signal, and a broadcast cable signal.

25. The radio receiver of claim 18 wherein at least one of:

the channel selector, the local oscillator, the analog front end, the digital clock generator and the digital section, are implemented as part of a system on a chip integrated circuit.

26. A method comprising:

controlling a digital clock frequency of a receiver to substantially two-thirds of a first received signal carrier frequency.

27. The method of claim 26 further comprising:

controlling a digital clock frequency of a receiver to substantially two-thirds of second received signal carrier frequency.

28. The method of claim 27 wherein the second received signal carrier frequency is not equal to the first received signal carrier frequency.