Radio receiver, system on a chip integrated circuit and methods for use therewith

• US 20070116150A1
• Filed: 11/22/2005
• Published: 05/24/2007
• Est. Priority Date: 11/22/2005
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Sigmatel LLC (NXP Semiconductors NV)
• Inventors: May, Michael, Lowe, Erich
• Granted Patent: US 7,672,403 B2
• Time in Patent Office: Days
• US Class Current: 375/322
• CPC Class Codes: H03D 3/007 by converting the oscillations into two quadrature related signals H03D3/245 takes precedence
• CPC Class Codes: H03J 1/0008 using a central processing unit, e.g. a microprocessor digital tuning in general H03J5/0245

Abstract

A system on a chip integrated circuit includes a first in-phase digital submodule and a first quadrature phase digital submodule such that the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal. A digital clock generator generates a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period. The plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.

Claims

1. A radio receiver comprising:

an analog front end for receiving a received radio signal containing a selected one of the plurality of channel signals, and for converting the selected one of the plurality of channel signals into an in-phase digital signal and a quadrature phase digital signal;

a digital section, operably coupled to the analog front end, for converting the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, the digital section having a first in-phase digital submodule and a first quadrature phase digital submodule; and

a digital clock generator, operably coupled to the first in-phase digital submodule and the first quadrature phase digital submodule, for generating a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period, wherein the plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.

2. The radio receiver of claim 1 wherein the plurality of first in-phase digital clock cycles are equal to the plurality of first quadrature phase digital clock cycles over the predetermined period.

3. The radio receiver of claim 1 wherein the digital clock generator generates a base clock signal at a base clock frequency that varies based on the selected one of the plurality of channel signals and wherein the plurality of first in-phase digital clock cycles and the plurality of first quadrature phase digital clock cycles are substantially constant over the predetermined period.

4. The radio receiver of claim 3 wherein the base clock frequency is less than a carrier frequency of the selected one of the plurality of channel signals and wherein the base clock frequency, and integer multiples of the base clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals.

5. The radio receiver of claim 1 wherein the digital section has a second in-phase digital submodule and a second quadrature phase digital submodule, and the digital clock generator, generates a second in-phase digital clock signal having a plurality of second in-phase digital clock cycles over a predetermined period and a second quadrature phase digital clock signal having a plurality of second quadrature phase digital clock cycles over the predetermined period, wherein the plurality of second in-phase digital clock cycles are substantially interleaved with the plurality of second quadrature phase digital clock cycles over the predetermined period.

6. The radio receiver of claim 1 wherein the digital clock generator substantially alternates between generating one or more of the plurality of first in-phase digital clock cycles with one or more of the plurality of first quadrature phase digital clock cycles over the predetermined period.

7. The radio receiver of claim 1 wherein the digital clock generator generates at least one of the plurality of first in-phase digital clock cycles in synchronism with at least one of the plurality of first quadrature phase digital clock cycles over the predetermined period.

8. The radio receiver of claim 1 wherein the received radio signal is one of:

a broadcast frequency modulated radio signal, a broadcast amplitude modulated radio signal, a broadcast satellite radio signal, IBOC digital radio signal, Bluetooth radio signal and a broadcast cable signal.

9. The radio receiver of claim 1 wherein at least one of:

the analog front end, the digital clock generator, and the digital section, are implemented as part of a system on a chip integrated circuit.

10. A system on a chip integrated circuit (IC) comprising:

a first in-phase digital submodule;

a first quadrature phase digital submodule; and

a digital clock generator, operably coupled to the first in-phase digital submodule and the first quadrature phase digital submodule, for generating a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period, wherein the plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period;

wherein the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal.

11. The system on a chip integrated circuit (IC) of claim 10 wherein the plurality of first in-phase digital clock cycles are equal to the plurality of first quadrature phase digital clock cycles over the predetermined period.

12. The system on a chip integrated circuit (IC) of claim 10 wherein the digital clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and wherein the plurality of first in-phase digital clock cycles and the plurality of first quadrature phase digital clock cycles are substantially constant over the predetermined period.

13. The system on a chip integrated circuit (IC) of claim 10 wherein the digital section has a second in-phase digital submodule and a second quadrature phase digital submodule, and the digital clock generator, generates a second in-phase digital clock signal having a plurality of second in-phase digital clock cycles over a predetermined period and a second quadrature phase digital clock signal having a plurality of second quadrature phase digital clock cycles over the predetermined period, wherein the plurality of second in-phase digital clock cycles are substantially interleaved with the plurality of second quadrature phase digital clock cycles over the predetermined period.

14. The system on a chip integrated circuit (IC) of claim 10 wherein the digital clock generator substantially alternates between generating one or more of the plurality of first in-phase digital clock cycles with one or more of the plurality of first quadrature phase digital clock cycles over the predetermined period.

15. The system on a chip integrated circuit (IC) of claim 10 wherein the digital clock generator generates at least one of the plurality of first in-phase digital clock cycles in synchronism with at least one of the plurality of first quadrature phase digital clock cycles over the predetermined period.

16. A method comprising:

generating a first in-phase digital clock signal having a plurality of first in-phase digital clock cycles over a predetermined period;

generating a first quadrature phase digital clock signal having a plurality of first quadrature phase digital clock cycles over the predetermined period,

wherein the plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.

17. The method of claim 16 wherein the plurality of first in-phase digital clock cycles are equal to the plurality of first quadrature phase digital clock cycles over the predetermined period.

18. The method of claim 16 further comprising:

generating a base clock signal at a base clock frequency that varies based on a control signal;

wherein the plurality of first in-phase digital clock cycles and the plurality of first quadrature phase digital clock cycles are substantially constant over the predetermined period.

19. The method of claim 16 further comprising:

generating a second in-phase digital clock signal having a plurality of second in-phase digital clock cycles over a predetermined period; and

generating a second quadrature phase digital clock signal having a plurality of second quadrature phase digital clock cycles over the predetermined period,

wherein the plurality of second in-phase digital clock cycles are substantially interleaved with the plurality of second quadrature phase digital clock cycles over the predetermined period.

20. The method of claim 16 wherein the plurality of first in-phase digital clock cycles substantially alternate with one or more of the plurality of first quadrature phase digital clock cycles over the predetermined period.

21. The method of claim 16 wherein at least one of the plurality of first in-phase digital clock cycles is generated in synchronism with at least one of the plurality of first quadrature phase digital clock cycles over the predetermined period.

22. An integrated circuit (IC) comprising:

a first digital submodule;

a second digital submodule; and

a digital clock generator, operably coupled to the first digital submodule and the second digital submodule, for generating a first digital clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period, wherein the plurality of first digital clock cycles and the plurality of second digital clock cycles are distributed substantially uniformly over the predetermined period;

wherein the first digital submodule and the second digital submodule are operable to produce at least one output signal based on at least one input signal.

23. The integrated circuit (IC) of claim 22 wherein the plurality of first digital clock cycles are equal to the plurality of second digital clock cycles over the predetermined period.

24. The integrated circuit (IC) of claim 22 wherein the digital clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and wherein the plurality of first digital clock cycles and the plurality of second digital clock cycles are substantially constant over the predetermined period.

25. The integrated circuit (IC) of claim 22 wherein the digital clock generator substantially alternates between generating one or more of the plurality of first digital clock cycles with one or more of the plurality of second digital clock cycles over the predetermined period.

26. The integrated circuit (IC) of claim 22 wherein the digital clock generator generates at least one of the plurality of first digital clock cycles in synchronism with at least one of the plurality of second digital clock cycles over the predetermined period.

27. The integrated circuit of claim 22 wherein the integrated circuit includes an in-phase signal path and a quadrature phase signal path and wherein the first digital submodule processes an in-phase signal and the second digital submodule processes a quadrature phase signal.

28. An integrated circuit (IC) comprising:

a first in-phase digital submodule;

a first quadrature phase digital submodule; and

a digital clock generator, operably coupled to the first in-phase digital submodule and the first quadrature phase digital submodule, for generating a first in-phase digital clock signal having a substantially constant number of first in-phase digital clock cycles over a predetermined period and a first quadrature phase digital clock signal having a substantially constant number of first quadrature phase digital clock cycles over the predetermined period;

wherein the first in-phase digital submodule and the first quadrature phase digital submodule are operable to produce at least one output signal based on at least one input signal.

29. The integrated circuit (IC) of claim 28 wherein the plurality of first in-phase digital clock cycles are equal to the plurality of first quadrature phase digital clock cycles over the predetermined period.

30. The integrated circuit (IC) of claim 28 wherein the plurality of first in-phase digital clock cycles are substantially interleaved with the plurality of first quadrature phase digital clock cycles over the predetermined period.

31. The integrated circuit (IC) of claim 28 wherein the digital clock generator substantially alternates between generating one or more of the plurality of first in-phase digital clock cycles with one or more of the plurality of first quadrature phase digital clock cycles over the predetermined period.

32. The integrated circuit (IC) of claim 28 wherein the digital clock generator generates at least one of the plurality of first in-phase digital clock cycles in synchronism with at least one of the plurality of first quadrature phase digital clock cycles over the predetermined period.