Insulated gate type semiconductor device and method for fabricating the same

• US 20070117329A1
• Filed: 01/16/2007
• Published: 05/24/2007
• Est. Priority Date: 02/19/2001
• Status: Active Grant

• Current Assignee: Renesas Semiconductor Package & Test Solutions Co., Ltd. (Renesas Electronics Corporation)
• Original Assignee: Renesas Eastern Japan Semiconductor Incorporated (Renesas Electronics Corporation)
• Inventors: Oishi, Kentaro, Inagawa, Hiroshi, Machida, Nobuo
• Granted Patent: US 7,361,557 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7821 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Claims

1-20. -20. (canceled)

21. A method of manufacturing a semiconductor device including a trench-gate type MISFET, comprising the steps of:

(a) preparing a semiconductor substrate having a first semiconductor layer thereon, said first semiconductor layer having a main surface, said semiconductor substrate having a back surface, and said semiconductor substrate and semiconductor layer having a first conduction type;

(b) forming a first insulation film over the main surface of the first semiconductor layer;

(c) forming trenches in the first insulating film and first semiconductor layer;

(d) forming gate insulating films of the MISFET on inner walls of the trenches;

(e) forming a conductive film over the first insulating film and on the gate insulating films;

(f) etching the conductive film on the first insulating film so as to form gate conductive layers of the MISFET on the gate insulating films, said gate conductive layers being electrically connected to each other;

(g) after the step (f), removing the first insulting film over the main surface of the first semiconductor layer, top surfaces of the gate conductive layers being positioned above the main surface of the first semiconductor layer;

(h) forming a base region of the MISFET having a second conduction type in the first semiconductor layer, said second conduction type being opposite to the first conduction type;

(i) forming a source region of the MISFET having the first conductive type on the semiconductor layer;

(j) forming a second insulating film over the gate conductive layers and the main surface of the first semiconductor layer;

(k) etching the second insulating film so as to form side wall spacers on side surfaces of the gate conductive layers;

(l) after the step (k), etching the main surface of the first semiconductor layer between adjacent gate conductive layers so as to form a contact hole, said contact hole contacting the source region and the base region; and

(m) forming a source conductive layer in the contact hole, said source conductive layer being electrically connected with the source region and the base region.

22. A method of manufacturing a semiconductor device according to claim 21, wherein in the step (1), the contact hole is formed in a self-alignment manner using the side wall spacers.

23. A method of manufacturing a semiconductor device according to claim 21, further comprising the step of:

(n) after the step (l), forming a contact layer in the contact hole, said contact layer having the second conduction type, and said contact layer and the base region being contacted to each other.

24. A method of manufacturing a semiconductor device according to claim 21, further comprising the step of:

(o) forming a drain electrode on the back surface of the semiconductor substrate, said drain electrode being electrically connected with the semiconductor substrate and the first semiconductor layer.

25. A method of manufacturing a semiconductor device including a trench-gate type MISFET, comprising the steps of:

(a) preparing a semiconductor substrate having a first semiconductor layer thereon, said first semiconductor layer having a main surface, and said semiconductor substrate having a back surface;

(b) forming a first insulating film over the main surface of the first semiconductor layer;

(c) forming trenches in the first insulating film and first semiconductor layer;

(d) forming gate insulating films of the MISFET on inner walls of the trenches;

(e) forming a conductive film over the first insulating film and on the gate insulating films;

(f) etching the conductive film on the first insulating film so as to form gate conductive layers of the MISFET on the gate films, said gate conductive layers being electrically connected to each other;

(g) after the step (f), removing the first insulating film over the main surface of the first semiconductor layer, top surfaces of the gate conductive layers being positioned above the main surface of the semiconductor layer;

(h) forming a second insulating film over the gate conductive layers and the main surface of the first semiconductor layer; and

(i) etching the second insulating film so as to form side wall spacers on side surfaces of the gate conductive layers.

26. A method of manufacturing a semiconductor device according to claim 25, further comprising the step of:

(j) after the step (i), etching the main surface of the first semiconductor layer between adjacent gate conductive layers so as to form a contact hole, said contact hole being formed in a self-alignment manner using the side wall spacers; and

(k) forming a source conductive layer in the contact hole.