METHODS OF FABRICATING HIGHLY CONDUCTIVE REGIONS IN SEMICONDUCTOR SUBSTRATES FOR RADIO FREQUENCY APPLICATIONS

• US 20070117345A1
• Filed: 01/23/2007
• Published: 05/24/2007
• Est. Priority Date: 11/20/2001
• Status: Active Grant

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Xie, Ya-Hong, Yeh, Chang-Ching, Tu, King-Ning
• Granted Patent: US 7,772,117 B2
• Time in Patent Office: Days
• US Class Current: 438/406
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/76227 the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.

Claims

1. A method of fabricating highly conductive regions in semiconductor substrates for radio frequency applications, comprising:

creating a moat on a surface of a Si (silicon) substrate using standard lithography techniques, followed by an anisotropic wet etching; and

depositing a multilayer metallic thin film into the moat.

2. The method of claim 1, wherein the anisotropic wet etching is performed in a solution of KOH (potassium hydroxide).

3. The method of claim 1, wherein the multilayer metallic thin film is a trilayer of Cr/Cu/Au (chromium/copper/gold) or Ti/Ni/Pd (titanium/nickel/palladium).

4. The method of claim 1, wherein the moat is comprised of one or more V-grooves created along a [110] direction on an (001) surface of the Si substrate.

5. The method of claim 4, wherein the V-grooves are prepared on both surfaces of the Si substrate for isolation purposes.

6. The method of claim 4, wherein the V-groove'"'"'s width is selected to give a depth of the V-groove that is about half the thickness of the Si substrate.

7. The method of claim 4, further comprising strengthening the V-grooves by a flow of molten solder into the V-grooves using a horizontal capillary effect.

8. The method of claim 7, wherein the solder is a lead-free alloy such as eutectic SnAg (tin-silver) or SnAgCu (tin-silver-cooper).

9. The method of claim 1, wherein the moat is comprised of one or more trenches.

10. The method of claim 9, wherein the multilayer metallic thin film comprises Cu (copper).

11. The method of claim 10, wherein the trench is filled entirely with Cu.

12. The method of claim 10, wherein the trench is plated with a layer of Cu and then filled with molten solder.

13. The method of claim 10, wherein the Cu is electro-plated into the trenches.

14. The method of claim 10, wherein the Cu is deposited by chemical vapor deposition (CVD).