Coiled circuit device with active circuitry and methods for making the same

• US 20070117392A1
• Filed: 01/17/2007
• Published: 05/24/2007
• Est. Priority Date: 06/06/2003
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Inventors: Smith, Joseph, Howell, Robert, Kirby, Christopher, Nathanson, Harvey, Storaska, Garrett
• Granted Patent: US 7,868,358 B2
• Time in Patent Office: Days
• US Class Current: 438/689
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

A device includes a coiling layer, a circuit device layer and active microelectronic circuitry fabricated on the circuit device layer. The coiling layer is formed onto a surface of and coupled to the circuit device layer. The coiling layer having intrinsic stresses which cause coiling of the coiling layer and the circuit device layer including the microelectronic circuitry as the circuit device layer is released from an underlying substrate. A coiled circuit device is formed.

Claims

1. A device comprising:

a coiling layer;

a circuit device layer;

active microelectronic circuitry fabricated on the circuit device layer.

2. The device of claim 1, wherein the circuit device layer comprises single crystal silicon.

3. The device of claim 2, wherein the active microelectronic circuitry is fabricated on the single crystal silicon.

4. The device of claim 1, wherein the coiling layer is formed onto a surface of and coupled to the circuit device layer, the coiling layer having intrinsic stresses which cause coiling of the coiling layer and the circuit device layer including the microelectronic circuitry as the circuit device layer is released from an underlying substrate.

5. The device of claim 1, wherein the active microelectronic circuitry comprises thin complementary metal oxide semiconductor (CMOS) circuitry.

6. The device of claim 1, wherein the coiling layer comprises nitride.

7. The device of claim 1, wherein the active microelectronic circuitry comprises:

one or more of a thin film battery, processor, memory, radio frequency receiver, radio frequency transmitter, micro-electronic mechanical systems (MEMS), capacitive storage system, antenna, and logic gates.

8. The device of claim 1, wherein the active microelectronic circuitry comprises:

a dipole antenna.

9. The device of claim 1, wherein the active microelectronic circuitry comprises:

one or more environmental sensors, wherein the environmental sensor includes one or more of a pollution and a chemical sensor.

10. The device of claim 1, wherein the coiling layer, the circuit device layer and the active microelectronic circuitry is less than 1000 angstroms (Å

) in thickness.

11. The device of claim 1, wherein the device ranges from 1 μ

m to 10000 μ

m in diameter, and ranges from 1 μ

m to 1 cm in length.

12. A method for fabricating a coiled circuit device, the method comprising:

oxidizing a first silicon on insulator wafer;

forming a double silicon on insulator wafer by bonding the oxidized first silicon on insulator wafer to a second silicon on insulator wafer, and removing the insulator and a buried oxide layer from the second silicon on insulator wafer;

fabricating complementary metal oxide semiconductor (CMOS) circuitry on a top silicon layer of the double silicon on insulator wafer;

depositing a passivating layer over the fabricated CMOS circuitry;

depositing a stress inducing layer on the deposited passivating layer;

etching a bottom silicon layer of the double silicon on insulator wafer thus releasing the fabricated CMOS circuitry, the passivating layer and the stress inducing layer, wherein a coil including the fabricated CMOS circuitry, the passivating layer and the stress inducing layer is formed.

13. The method of claim 12, further comprising:

etching vias around the fabricated CMOS circuitry, wherein the vias are etched to the bottom silicon layer.

14. The method of claim 12, further comprising:

depositing an silicon dioxide layer on sidewalls of the fabricated CMOS circuitry, the passivating layer and the stress inducing layer.

15. The method of claim 12, wherein etching the bottom silicon layer comprises:

undercutting the bottom silicon layer from one end such that the fabricated CMOS circuitry, the passivating layer and the stress inducing layer, above the bottom silicon layer, coil in a direction of the undercutting.

16. The method of claim 12, wherein the stress inducing layer comprises stressed nitride.

17. The method of claim 12, wherein the coiling layer is selected from a material having a different coefficient of thermal expansion than silicon oxide.

18. The method of claim 12, wherein the first silicon on insulator wafer comprises a polysilicon on insulator wafer.

19. The method of claim 18, further comprising:

undercutting the polysilicon layer from one end such that the fabricated CMOS circuitry, the passivating layer and the stress inducing layer, above the polysilicon layer, coil in a direction of the undercutting.

20. A coiled circuit device comprising:

a coiling layer including stressed silicon nitride;

a circuit device layer, wherein the circuit device layer comprises single crystal silicon; and

active microelectronic circuitry fabricated on the single crystal silicon, wherein the active microelectronic circuitry comprises thin complementary metal oxide semiconductor (CMOS) circuitry, and the coiling layer is formed onto a surface of and coupled to the circuit device layer, the coiling layer having intrinsic stresses which cause coiling of the coiling layer and the circuit device layer when the circuit device layer is released from an underlying substrate.

21. The coiled circuit device of claim 20, wherein the active microelectronic circuitry comprises:

one or more of a thin film battery, processor, memory, radio frequency receiver, radio frequency transmitter, micro-electronic mechanical systems (MEMS) capacitive storage system, antenna and logic gates.

22. The coiled circuit device of claim 20, wherein the active microelectronic circuitry comprises:

a dipole antenna.

23. The coiled circuit device of claim 20, wherein the active microelectronic circuitry comprises:

one or more environmental sensors, wherein the environmental sensor includes one or more of a pollution and chemical sensor.

24. The coiled circuit device of claim 20, wherein the coiling layer, the circuit device layer and the active microelectronic circuitry is less than 1000 angstroms (Å

) in thickness.

25. The coiled circuit device of claim 20, wherein the coiled circuit device ranges from 1 μ

m to 10000 μ

m in diameter, and ranges from 1 μ

m to 1 cm in length.

26. A method for fabricating a coiled circuit device, comprising:

depositing a silicon oxide layer on a silicon substrate;

depositing a device layer over the deposited silicon oxide layer;

forming active circuitry on the device layer;

depositing a stress inducing layer on the active circuitry;

releasing the device layer having the active circuitry deposited with the stress inducing layer by etching the silicon oxide layer from the silicon substrate, wherein the releasing causing the device layer having the active circuitry deposited with the stress inducing layer to coil forming a plurality of concentric circles.

27. The method of claim 26, wherein forming the active circuitry on the device layer comprises:

depositing a photoresist layer on a portion of the device layer;

positively doping a portion of the device layer that is not deposited with the photoresist layer;

stripping the deposited photoresist layer, wherein positively charged regions separated by one or more negatively charged channels are formed.

28. The method of claim 26, wherein the forming the active circuitry on the device layer comprises:

depositing a first photoresist layer on a portion of the device layer;

etching a portion of the device layer to form one or more trenches; and

depositing oxide in the one or more formed trenches.

29. The method of claim 28, wherein the forming the active circuitry further comprising:

depositing a second phototoresist layer on a portion of the device layer and some of the one or more trenches including the oxide;

negatively doping the device layer not deposited with the photoresist layer to form negative channel regions;

depositing a third phototoresist layer on a portion of the negatively doped device layer and some of the one or more trenches including the oxide;

removing the second photoresist layer from the portion of the device layer and some of the one or more trenches including the oxide; and

positively doping the portion of the device layer from which the second photo resist layer is removed.

30. The method of claim 29, wherein the forming the active circuitry further comprising:

depositing gate oxide layers on the negatively doped device layer and the positively doped device layer;

depositing gate polysilicon on the gate oxide layers;

implanting a negatively doped drain in the positively doped device layer;

implanting a positively doped drain in the negatively doped device layer;

forming spacers adjacent to the deposited gate polysilicon; and

implanting and activating positive regions in the positively doped device layer; and

implanting and activating negative regions in the negatively doped device layer.

31. The method of claim 30, wherein the stress inducing layer is deposited on the active circuitry formed by the implanted and activated positive and negative regions, the deposited gate polysilicon, and the formed spacers.

32. The method of claim 31, further comprising:

etching metal contacts for the active circuitry.

33. The method of claim 26, further comprising:

forming dielectric buttons on a portion of the active circuitry to isolate conductive material from the active circuitry.

34. A coiled sensor comprising:

a coiled device layer that forms a plurality of concentric cylinders, wherein the device circuit layer is at or between 50 nanometers and 75 nanometers thick, the coiled device layer including;

a power supply;

a memory;

a processor; and

a transmitter or receiver, wherein an outer diameter of the coiled sensor is at or between 75 and 150 micrometers and a length is at or between 1 millimeter and 10 millimeters, when coiled.