Packet switch having a crossbar switch that connects multiport receiving and transmitting elements

• US 20070118677A1
• Filed: 05/13/2005
• Published: 05/24/2007
• Est. Priority Date: 05/13/2005
• Status: Abandoned Application

• Current Assignee: Preescale Semiconductor Incorporated
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Wilcox, Jeffrey, Swartzentruber, Ron
• Application Number:
  US11/129,250
• Publication Number:
  US 20070118677A1
• Time in Patent Office: Days
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation

Abstract

An integrated circuit on which are implemented a number of devices that conform to the Rapidio network architecture. Included in the integrated circuit are two addressed RapidIO devices and switching devices which provide 24 switching ports. The devices have a packet receiving side and a packet transmitting side; the packet receiving side of each of the devices is connected by 128-bit wide paths termed poles its own packet transmitting side and each of the other transmitting sides. Features of the integrated circuit include centralized multicasting and configuration control for all of the devices on the integrated circuit, provisions for having more than one address in a RapidIO device, techniques for defining the address space routed by a routing table, techniques for managing congestion, and advanced buffer management techniques.

Claims

1. Switching apparatus for switching packets of data, the apparatus comprising:

a plurality of devices, each device having a receiving part which receives packets from a plurality of sources and an outputting part which outputs packets to a plurality of destinations specified by destination specifiers in the packets;

a plurality of output data paths, there being for each device separate output paths connecting the device'"'"'s input part to the device'"'"'s output part and the output parts for each of the other devices; and

routing apparatus which responds to the destination specifier by routing the packet from the receiving part via the output data path of the plurality which connects the receiving part to the outputting part which outputs packets to the specified destination.

8. The switching apparatus set forth in claim 1 wherein:

the routing apparatus has a portion in each of the receiving parts.

9. The switching apparatus set forth in claim 8 wherein:

each portion includes apparatus that defines an address space of addresses that are routed by the portion.

10. The switching apparatus set forth in claim 1 wherein

the packets have a plurality of priorities;

and

the receiving part further comprises;

an arbiter that arbitrates among received packets for access to the output data paths according to each packet'"'"'s priority.

11. The switching apparatus set forth in claim 10 wherein:

the arbiter treats a packet that is stalled in the receiving part as having a stalled priority that is higher than the packet'"'"'s priority.

12. The switching apparatus set forth in claim 1 wherein:

the switching apparatus obeys a packet network architecture that has endpoints and switches, each endpoint having an address;

the destination specifiers in the packets specify addresses of endpoints; and

the switching apparatus further comprises;

an endpoint, the endpoint providing packets to the receiving part of a device of the plurality and receiving packets from the outputting part of the device.

13. The switching apparatus set forth in claim 1 wherein

the switching apparatus obeys a packet network architecture that defines maintenance packets;

and

the switching apparatus further comprises;

a configuration interface that responds to maintenance packets that arrive in the switching apparatus to configure the routing apparatus and/or the devices of the plurality.

14. The switching apparatus set forth in claim 1 wherein

the switching apparatus obeys a packet network architecture that defines packets that are to be multicast to a plurality of multicast destinations;

and

the switching apparatus further comprises;

a multicast unit to which all packets that are to be multicast are routed, the multicast unit routing being coupled to the plurality of output data paths and routing copies of the packets to be output to the outputting parts which output the copies to the multicast destinations of the plurality.

15. The switching apparatus set forth in claim 14 wherein:

the multicast unit is a component of a device of the plurality.

16. The switching apparatus set forth in claim 8 wherein:

the plurality of devices and the plurality of output paths are implemented in a single integrated circuit.

17. The switching apparatus set forth in claim 16 wherein:

the routing apparatus is also implemented in the single integrated circuit.

2. Apparatus which implements a plurality of packet network devices in an integrated circuit, the packet network devices being defined by an architecture for a packet network that has addressable and non-addressable devices and the apparatus comprising:

an addressable device in the integrated circuit which is a destination for packets defined by the architecture; and

a non-addressable device in the integrated circuit which routes packets to their destinations,

the non-addressable device being coupled to the addressable device and responding to a packet whose destination is the addressable device by routing the packet thereto and responding to a packet whose destination is not the addressable device by routing the packet as required by the destination.

23. The apparatus set forth in claim 2 further comprising;

a plurality of the addressable devices.

24. The apparatus set forth in claim 2 further comprising;

a plurality of the non-addressable devices.

25. The apparatus set forth in claim 24 further comprising:

a plurality of the addressable devices.

26. The apparatus set forth in claim 2 further comprising:

routing apparatus which is distributed across the plurality of packet network devices.

27. The apparatus set forth in claim 2 further comprising;

a configuration interface that configures the devices of the plurality in response to configuration packets.

28. The apparatus set forth in claim 2 further comprising:

a multicaster which receives multicast packets of the packets and routes the multicast packets to the packet network devices.

3. Apparatus which implements a plurality of packet network devices in an integrated circuit, the apparatus comprising:

the plurality of packet network devices; and

a device manager which performs functions for each of the packet network devices as required by that packet network device.

4. The apparatus set forth in claim 3 wherein:

the functions include configuration functions that are performed in response to configuration packets specifying configuration operations to be performed on individual ones of the network devices.

5. The apparatus set forth in claim 3 wherein:

the packet network has an architecture which defines certain packets as multicast packets;

the devices have a plurality of input ports for receiving packets and a plurality of ports for outputting received packets; and

the functions include receiving multicast packets from any of the plurality of input ports, making copies of the multicast packets, and providing the copies to ports of the plurality of output ports.

6. A method of preventing a packet from being stalled in apparatus wherein packets having differing priorities contend for access to a resource, the access to the resource being controlled by an arbiter and the method including the steps of:

establishing a threshold time for determining whether a particular packet is stalled; and

responding in the arbiter when the threshold time is exceeded by treating the particular packet during arbitration for the resource as if the particular packet had a higher priority.

29. The method set forth in claim 6 wherein:

the stalled packet is contained in a buffer and

the method further comprises the step of;

determining a degree of utilization of the buffer; and

in the step of establishing a threshold time, the threshold time is determined at least in part by the degree of utilization of the buffer.

30. The method set forth in claim 29 wherein

certain of the packets may be dropped and

the method further comprises the step performed when the resource is not available for access of:

responding in the arbiter when the threshold time is exceeded and the packet may be dropped by dropping the packet.

31. The method set forth in claim 6 wherein

certain of the packets may be dropped and

the method further comprises the step performed when the resource is not available for access of:

responding in the arbiter when the threshold time is exceeded and the packet may be dropped by dropping the packet.

32. The method set forth in claim 6 wherein:

in the step of responding in the arbiter, the arbiter gives stalled packets a higher priority than all but the highest-priority non-stalled packets.

33. The method set forth in claim 32 wherein:

the highest-priority non-stalled packets are flow control packets.

34. The method set forth in claim 6 wherein:

the arbiter gives all packets that the arbiter treats as having the higher priority round-robin access to the resource.

35. A storage device which may be accessed by a processor, the storage device being characterized in that:

the storage device contains code which, when executed by the processor, performs the method set forth in claim 6.

7. Apparatus used with a routing table whose indexes have a first length to define an address space of addresses which the routing table will route, the addresses in the address space having a second length that is longer than the first length and the apparatus comprising:

a processing unit having access to memory, the memory containing

the routing table;

a base value; and

an address having the second length,

the processing unit using non-index bits of the address that are not used to index the routing table and the base value to determine whether the address belongs to the address space, and if the address does belong to the address space, using index bits of the address to index the routing table.

41. The apparatus set forth in claim 7 wherein:

the routing table is in apparatus with settable configuration memory; and

the memory that contains the base value is configuration memory.

42. The apparatus set forth in claim 7 further comprising:

a mask value in the memory;

the processing unit determining whether the address belongs to the address space by masking at least some of the non-index bits and comparing the result of the masking with the base value.

43. The apparatus set forth in claim 42 wherein:

the routing table is in apparatus with settable configuration memory; and

the memory that contains the base value and the mask value is configuration memory.

44. The apparatus set forth in claim 7 further comprising:

an offset value in the memory,

the processing unit determining whether the address belongs to the address space by using the offset value to determine the location of the index bits in the address.

45. The apparatus set forth in claim 44 wherein:

the routing table is in apparatus with settable configuration memory; and

the memory that contains the base value and the offset value is configuration memory.

46. The apparatus set forth in claim 44 further comprising:

a mask value in the memory;

the processing unit determining whether the address belongs to the address space by masking at least some of the non-index bits and comparing the result of the masking with the base value.

47. The apparatus set forth in claim 44 wherein:

the routing table is in apparatus with settable configuration memory; and

the memory that contains the base value, the offset value, and the mask value is configuration memory.

18. A method of switching packets in a switching apparatus that includes

a plurality of devices, each device having a receiving part which receives packets from a plurality of sources and an outputting part which outputs packets to a plurality of destinations specified by destination specifiers in the packets and

a plurality of output data paths, there being for each device separate output paths connecting the device'"'"'s input part to the device'"'"'s output part and the output parts for each of the other devices,

the method comprising the steps performed in a receiving part of:

receiving packets in the receiving part; and

routing each packet to an outputting part via the output data path to the output part which outputs the packet to the destination specified in the packet'"'"'s destination specifier.

19. The method set forth in claim 18 further comprising the step of:

arbitrating among the received packets for access to the output data path.

20. The method set forth in claim 19 wherein:

each of the packets has a priority; and

in the step of arbitrating, taking the priority of the packets into account.

21. The method set forth in claim 20 wherein:

in the step of arbitrating, giving a packet that is stalled in the receiving part a stalled priority which is higher than the packet'"'"'s priority.

22. A storage device which may be accessed by a processor, the storage device being characterized in that:

the storage device contains code which, when executed by the processor, performs the method set forth in claim 18.

36. Apparatus for ensuring that lower-priority packets receive access to a shared resource, the apparatus comprising:

a plurality of queues, the packets at the heads of the queues contending for access to the shared resource;

for each one of the queues, a stall indicator that indicates whether the packet at the head of the queue is stalled; and

an arbiter for the resource that arbitrates among the packets at the heads of the queues according to the priorities of the packets, the arbiter responding to the stall indicator by treating the packet at the head of the queue as having a stalled priority that is higher than others of the priorities.

37. The apparatus for ensuring that lower-priority packets receive access set forth in claim 36 wherein:

the arbiter gives packets having the stalled priority round-robin access to the shared resource.

38. The apparatus for ensuring that lower-priority packets receive access set forth in claim 36 wherein the stall indicator comprises:

a cycle counter that determines how long a packet has remained at the head of a queue; and

a queue utilization indicator that indicates how full the queue is, the arbiter responding to the cycle counter as determined by the queue utilization indicator.

39. The apparatus for ensuring that lower priority packets receive access set forth in claim 36 wherein:

certain of the packets are flow control packets and

the stalled priority is lower only than the priority for flow control packets.

40. The apparatus for ensuring that lower priority packets receive packets set forth in claim 36 wherein:

certain of the packets may be dropped and

the arbiter responds when the resource is not available for access, the stall indicator indicates that the packet is stalled, and the packet may be dropped by dropping the packet.

48. A method of routing addresses that have a first length and belong to a first address space, the method employing a routing table whose indexes have a second length that is shorter than the first length and the method comprising the steps of:

using a non-index portion of the address and the base value to determine whether the address belongs to the address space; and

if the address does belong to the address space, using an index portion of the address to index the routing table.

49. The method of routing addresses set forth in claim 48 wherein the step of using the non-index portion and the base value comprises:

masking the non-index portion with a mask; and

comparing the result of the masking with the base value.

50. The method of routing addresses set forth in claim 48 wherein the method further comprises the step of:

using an offset value to determine the location of the index portion of the address.

51. The method of routing addresses set forth in claim 50 wherein the step of using the non-index portion and the base value comprises:

masking the non-index portion with a mask; and

comparing the result of the masking with the base value.

52. A storage device which may be accessed by a processor, the storage device being characterized in that:

the storage device contains code which, when executed by the processor, performs the method set forth in claim 48.