Memory system for legacy hosts

• US 20070118713A1
• Filed: 11/22/2005
• Published: 05/24/2007
• Est. Priority Date: 11/22/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Gonzalez, Carlos, Cedar, Yoram, Conley, Kevin, Schroter, Charles, Guterman, Daniel, Barrocas, Milton
• Granted Patent: US 7,739,472 B2
• Time in Patent Office: Days
• US Class Current: 711/170
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.

Claims

1. A memory device, comprising:

at least one memory chip with a first set of memory and communication characteristics;

a connector for coupling to a legacy host;

said legacy host designed to operate with a legacy memory device having a second set of memory and communication characteristics and not designed to operate directly with said at least one memory chip;

an interface circuit coupled between said connector and said at least one memory chip to enable said memory device to emulate said legacy memory when said legacy host is coupled to said connector; and

wherein said interface circuit resolves at least one difference that exists between the first and second sets of memory and communication characteristics, said at least one difference selected from the group consisting essentially of error correction code, memory block size, number of bits stored in each memory cell, and status information.

2. The memory device as in claim 1, wherein:

said memory device comprises multi-bit memory cells and said legacy host is designed to operate the legacy memory device having single-bit memory cells.

3. The memory device as in claim 1, wherein:

said at least one difference includes an error correction code (ECC) among said second set of operating characteristics; and

said interface circuit includes an ECC computing module for processing said ECC.

4. The memory device as in claim 1, wherein:

said at least one difference includes a status bit indicating a memory operating condition among said first set of operating characteristics; and

said interface circuit includes;

a directory stored in said at least one memory chip; and

a circuit for storing one or an alternative state of said status bit in said directory responsive to the presence or absence of said memory operating condition.

5. The memory device as in claim 1, wherein:

said at least one difference includes memory block size where said memory device has a memory block size larger than that of said legacy memory device.

6. The memory device as in claim 1, wherein:

said at least one difference includes number of bits stored in each memory cell where said memory device stores more bits per memory cell than said legacy memory device the legacy host was designed to operate with.

7. The memory device as in claim 1, wherein said interface circuit further comprises:

an asynchronous host interface unit for interfacing with said host;

an asynchronous memory chip interface unit for interfacing with said at least one memory chips; and

a control unit for controlling said asynchronous host interface unit and said asynchronous memory chip interface unit.

8. The memory device as in claim 7, wherein said interface circuit further comprises:

a set of codes executed by said control unit to resolve differences that exist between the first and second sets of memory and their communication characteristics.