Information processing apparatus and processor and control method

• US 20070118773A1
• Filed: 04/14/2006
• Published: 05/24/2007
• Est. Priority Date: 11/18/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tsuji, Kazuhiko
• Granted Patent: US 7,562,240 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to one embodiment, an information processing apparatus includes a main body in which a battery is mountable and a processor provided in the main body and including a first core and a second core. The information processing apparatus further comprises a power supply controller that executes a process for setting the processor in one of a multi-core mode in which the first core and the second core are operable and a single-core mode in which one of the first core and the second core is operable, in accordance with rating information indicative of a performance of the battery mounted in the main body, which is stored in the battery.

Claims

1. An information processing apparatus comprising:

a main body adapted to receive a battery;

a processor provided in the main body, the processor including a first core and a second core; and

a power supply controller to execute a process for setting the processor in one of a plurality of operating modes based on rating information indicative of a performance of the battery, the plurality of operating modes include (i) a multi-core mode in which the first core and the second core are operable and (ii) a single-core mode in which one of the first core and the second core is operable.

2. The information processing apparatus according to claim 1, wherein the power supply controller obtains the rating information from the battery.

3. The information processing apparatus according to claim 2, wherein the rating information is stored in a non-volatile memory housed in the battery, the battery being mounted to the main body.

4. The information processing apparatus according to claim 1, wherein the rating information is indicative of a maximum discharge current value of the battery.

5. The information processing apparatus according to claim 1, wherein the rating information is indicative of a maximum discharge current value of the battery, and

the power supply controller sets the processor in the single-core mode in a case where the maximum discharge current value of the battery is less than a reference value, and sets the processor in the multi-core mode in a case where the maximum discharge current value of the battery is not less than the reference value.

6. The information processing apparatus according to claim 1, wherein the power supply controller includes means for determining whether an external power supply is coupled to the main body, and means for setting the processor in the multi-core mode when the external power supply is coupled to the main body.

7. The information processing apparatus according to claim 6, wherein the processor is set in the multi-core mode when the external power supply is coupled to the main body regardless of the rating information of the battery.

8. The information processing apparatus according to claim 1, wherein the first core of the processor is adapted to operate independently from the second core of the processor.

9. An information processing apparatus comprising:

a main body in which a battery is mountable;

a processor provided in the main body and including a first core and a second core;

means for acquiring rating information indicative of a performance of the battery after the battery is mounted in the main body, the rating information being stored in the battery mounted in the main body; and

control means for executing a process for setting, in accordance with the acquired rating information, the processor in one of (i) a multi-core mode in which both the first core and the second core operate and (ii) a single-core mode in which one of the first core and the second core operates.

10. The information processing apparatus according to claim 9, wherein the rating information is indicative of a maximum discharge current value of the battery.

11. The information processing apparatus according to claim 9, wherein the rating information is indicative of a maximum discharge current value of the battery, and

the control means sets the processor in the single-core mode in a case where the maximum discharge current value of the battery is less than a reference value, and sets the processor in the multi-core mode in a case where the maximum discharge current value of the battery is not less than the reference value.

12. The information processing apparatus according to claim 9, wherein the control means determines, when the main body is powered on, whether an external power supply is connected to the main body, and sets the processor in the multi-core mode, regardless of the acquired rating information, when it is determined that the external power supply is connected to the main body.

13. A method for controlling an operation of a processor including a first core and a second core and provided in a main body adapted to receive a battery, comprising:

acquiring rating information indicative of a performance of the battery; and

executing a control process for setting, in accordance with the acquired rating information, the processor in one of a multi-core mode in which the first core and the second core operate and a single-core mode in which one of the first core and the second core operates.

14. The method according to claim 13, wherein the rating information is stored within and acquired from the battery.

15. The method according to claim 14, wherein the rating information is indicative of a maximum discharge current value of the battery.

16. The method according to claim 15, wherein the execution of the control process sets the processor in the single-core mode when the maximum discharge current value of the battery is less than a reference value, and sets the processor in the multi-core mode when the maximum discharge current value of the battery is not less than the reference value.

17. The method according to claim 13, further comprising:

determining whether an external power supply is connected to the main body; and

setting the processor in the multi-core mode, regardless of the acquired rating information upon determining that the external power supply is connected to the main body.

18. The method according to claim 14, wherein the rating information is acquired from the battery that is mounted to the main body.