Digital demodulating apparatus, controlling method of the apparatus, computer program product for the apparatus, recording medium recording thereon the product, and digital receiver

• US 20070118788A1
• Filed: 11/17/2006
• Published: 05/24/2007
• Est. Priority Date: 11/21/2005
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kaiki, Nobuyoshi
• Granted Patent: US 7,861,133 B2
• Time in Patent Office: Days
• US Class Current: 714/755
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/0075 Transmission of coding parameters to receiver H04L1/0023 takes precedence
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER

Abstract

A digital demodulating apparatus comprises circuit elements constituting a tuner that performs channel select processing to an interleaved received signal, and a demodulator that demodulates the received signal; a deinterleaving section that deinterleaves the interleaved received signal; an error correcting section that corrects errors in the received signal deinterleaved by the deinterleaving section; and a circuit element controlling section that controls an operation of at least one of the circuit elements. The circuit element controlling section estimates the quantity of hypothetical errors in the received signal caused by a control of a circuit element. The circuit element controlling section judges from the estimated quantity of hypothetical errors whether the error correcting section can correct errors in the received signal caused by the control of the circuit element. The circuit element controlling section controls the circuit element so as to decrease the quantity of errors in the received signal caused by the control of the circuit element, when the circuit element controlling section decided that the error correcting section can not correct the errors in the received signal.

Claims

1. A digital demodulating apparatus comprising:

a plurality of circuit elements constituting a tuner that performs channel select processing to a received signal that has been interleaved, and a demodulator that performs demodulation processing to the received signal from the tuner;

a deinterleaving section that performs deinterleave processing to the interleaved received signal from the tuner;

an error correcting section that corrects errors included in the received signal that has been deinterleaved by the deinterleaving section; and

a circuit element controlling section that controls an operation of at least one of the plurality of circuit elements,

the circuit element controlling section estimating the quantity of hypothetical errors to be generated in the received signal due to a control of an operation of a circuit element,

the circuit element controlling section judging from the estimated quantity of hypothetical errors whether or not the error correcting section can correct errors to be included in the received signal due to the control of the operation of the circuit element,

the circuit element controlling section controlling the operation of the circuit element so as to decrease the quantity of errors to be generated in the received signal due to the control of the operation of the circuit element, when the circuit element controlling section has decided that the error correcting section can not correct the errors to be included in the received signal.

2. The apparatus according to claim 1, wherein the circuit element controlling section changes the quantity of the control of the operation of the circuit element so as to decrease the quantity of errors to be generated in the received signal due to the control of the operation of the circuit element, when the circuit element controlling section has decided that the error correcting section can not correct the errors to be included in the received signal, and

the circuit element controlling section does not change the quantity of the control of the operation of the circuit element when the circuit element controlling section has decided that the error correcting section can correct the errors to be included in the received signal.

3. The apparatus according to claim 2, wherein the circuit element controlling section controls the circuit element so as not to change the operation of the circuit element, when the circuit element controlling section has decided that the error correcting section can not correct the errors to be included in the received signal.

4. The apparatus according to claim 1, wherein the control to be performed by the circuit element controlling section is a control to change the power consumption of the circuit element.

5. The apparatus according to claim 1, wherein the circuit element controlling section comprises a CN ratio estimating section that estimates a CN ratio of the received signal in which the hypothetical errors are to be generated due to the control of the operation of the circuit element.

6. The apparatus according to claim 5, wherein the circuit element controlling section comprises a threshold deriving section that derives a threshold of a CN ratio of the received signal, and

the circuit element controlling section decides that the error correcting section can correct the hypothetical errors to be included in the received signal due to the control of the operation of the circuit element by the circuit element controlling section, when a CN ratio of the received signal estimated by a CN ratio estimating section exceeds the threshold of the CN ratio of the received signal derived by the threshold deriving section.

7. The apparatus according to claim 6, wherein the threshold deriving section derives the threshold of the CN ratio of the received signal on the basis of at least one of a demodulation method, a coding rate, and an effective symbol length of the received signal.

8. The apparatus according to claim 7, wherein the threshold deriving section is provided in the tuner, and

the tuner receives, from the demodulator, information on at least one of the demodulation method, the coding rate, and the effective symbol length of the received signal.

9. The apparatus according to claim 1, wherein the circuit element controlling section comprises an error quantity deriving section that derives the quantity of errors before control, included in the received signal before the control of the operation of the circuit element, and

the circuit element controlling section judges from the estimated quantity of hypothetical errors and the quantity of errors before control derived by the error quantity deriving section whether or not the error correcting section can correct errors to be included in the received signal.

10. The apparatus according to claim 9, wherein the error quantity deriving section comprises an error rate deriving section that derives an error rate of the received signal before the control of the operation of the circuit element by the circuit element controlling section.

11. The apparatus according to claim 9, wherein the error quantity deriving section comprises a deviation deriving section that derives a deviation, from a specified value, of constellation of the received signal before the control of the operation of the circuit element by the circuit element controlling section.

12. The apparatus according to claim 1, wherein the circuit element controlling section comprises a timing determining section that determines a timing at which the circuit element controlling section controls the operation of the circuit element.

13. The apparatus according to claim 12, further comprising a wave equalizing section that performs wave equalization on the basis of reliability of a scattered pilot signal included in the received signal at the timing for controlling the circuit element, determined by the timing determining section.

14. The apparatus according to claim 13, wherein the timing determining section and the wave equalizing section are provided in the tuner and the demodulator, respectively, and

the demodulator receives, from the tuner, information on the timing for controlling the circuit element, determined by the timing determining section.

15. The apparatus according to claim 12, wherein the timing determining section determines the timing for controlling the operation of the circuit element such that an error to be included in the received signal due to the control of the operation of the circuit element is put at a leading edge of one symbol included in the received signal.

16. The apparatus according to claim 12, wherein the circuit element controlling section further comprises a performance changing section that changes the error correction performance of the error correcting section on the basis of reliability of the received signal at the timing for controlling the circuit element, determined by the timing determining section.

17. The apparatus according to claim 16, wherein the timing determining section and the error correcting section are provided in the tuner and the demodulator, respectively, and

the demodulator receives, from the tuner, information on the timing for controlling the circuit element, determined by the timing determining section.

18. The apparatus according to claim 1, wherein the tuner comprises an RF amplifier section, a mixer section, a filter section, an IF amplifier section, and a VCO-PLL section, and

at least one of the RF amplifier section, the mixer section, the filter section, the IF amplifier section, and the VCO-PLL section, is to be controlled by the circuit element controlling section.

19. The apparatus according to claim 1, wherein the circuit element controlling section controls the circuit element such that regions occupied by errors to be generated due to a plurality of controls by the circuit element controlling section do not overlap each other in the deinterleaved received signal.

20. The apparatus according to claim 19, wherein the deinterleave processing to be performed by the deinterleaving section is time deinterleave processing in which a plurality of symbols included in the received signal are temporally rearranged, and

the number of times of controls of the operation of the circuit element by the circuit element controlling section in a range of a time interleaving length is not more than one.

21. The apparatus according to claim 1, wherein the deinterleave processing to be performed by the deinterleaving section is time deinterleave processing in which a plurality of symbols included in the received signal are temporally rearranged;

the circuit element controlling section comprises an error symbol specifying section that specifies an error symbol in which a hypothetical error is generated due to the control of the operation of the circuit element; and

the circuit element controlling section judges from the quantity of hypothetical errors estimated by the circuit element controlling section and the error symbol specified by the error symbol specifying section whether or not the error correcting section can correct errors to be included in the received signal due to a plurality of times of controls by the circuit element controlling section when the circuit element controlling section performs the plurality of times of controls in a range of a time interleaving length.

22. A controlling method of a digital demodulating apparatus comprising a plurality of circuit elements constituting a tuner that performs channel select processing to a received signal that has been interleaved, and a demodulator that performs demodulation processing to the received signal from the tuner;

a deinterleaving section that performs deinterleave processing to the interleaved received signal from the tuner;

an error correcting section that corrects errors included in the received signal that has been deinterleaved by the deinterleaving section; and

a circuit element controlling section that controls an operation of at least one of the plurality of circuit elements,

the method comprising;

an estimating step of estimating the quantity of hypothetical errors to be generated in the received signal due to a control of an operation of a circuit element by the circuit element controlling section;

a correction possibility judging step of judging from the quantity of hypothetical errors estimated in the estimating step whether or not the error correcting section can correct errors to be included in the received signal due to the control of the operation of the circuit element by the circuit element controlling section; and

a circuit element controlling step of allowing the circuit element controlling section to control the operation of the circuit element so as to decrease the quantity of errors to be generated in the received signal due to the control of the operation of the circuit element by the circuit element controlling section, when it was decided in the correction possibility judging step that the error correcting section can not correct errors to be included in the received signal.

23. The method according to claim 22, wherein the method further comprises an error rate deriving step of deriving an error rate of the received signal before the control of the operation of the circuit element by the circuit element controlling section, and

it is judged in the correction possibility judging step from the quantity of hypothetical errors estimated in the estimating step and the error rate before control, derived in the error rate deriving step, whether or not the error correcting section can correct errors to be included in the received signal.

24. The method according to claim 22, wherein the deinterleave processing to be performed by the deinterleaving section is time deinterleave processing in which a plurality of symbols included in the received signal are temporally rearranged, and

the number of times of controls of the operation of the circuit element by the circuit element controlling section in a range of a time interleaving length is not more than one.

25. A computer program product for a digital demodulating apparatus comprising a plurality of circuit elements constituting a tuner that performs channel select processing to a received signal that has been interleaved, and a demodulator that performs demodulation processing to the received signal from the tuner;

a deinterleaving section that performs deinterleave processing to the interleaved received signal from the tuner;

an error correcting section that corrects errors included in the received signal that has been deinterleaved by the deinterleaving section; and

a circuit element controlling section that controls an operation of at least one of the plurality of circuit elements,

the product causing the apparatus to perform;

an estimating step of estimating the quantity of hypothetical errors to be generated in the received signal due to a control of an operation of a circuit element by the circuit element controlling section;

a correction possibility judging step of judging from the quantity of hypothetical errors estimated in the estimating step whether or not the error correcting section can correct errors to be included in the received signal due to the control of the operation of the circuit element by the circuit element controlling section; and

a circuit element controlling step of allowing the circuit element controlling section to control the operation of the circuit element so as to decrease the quantity of errors to be generated in the received signal due to the control of the operation of the circuit element by the circuit element controlling section, when it was decided in the correction possibility judging step that the error correcting section can not correct errors to be included in the received signal.

26. A computer-readable recording medium recording thereon a computer program product for a digital demodulating apparatus comprising a plurality of circuit elements constituting a tuner that performs channel select processing to a received signal that has been interleaved, and a demodulator that performs demodulation processing to the received signal from the tuner;

a deinterleaving section that performs deinterleave processing to the interleaved received signal from the tuner;

an error correcting section that corrects errors included in the received signal that has been deinterleaved by the deinterleaving section; and

a circuit element controlling section that controls an operation of at least one of the plurality of circuit elements,

the product causing the apparatus to perform;

an estimating step of estimating the quantity of hypothetical errors to be generated in the received signal due to a control of an operation of a circuit element by the circuit element controlling section;

a correction possibility judging step of judging from the quantity of hypothetical errors estimated in the estimating step whether or not the error correcting section can correct errors to be included in the received signal due to the control of the operation of the circuit element by the circuit element controlling section; and

a circuit element controlling step of allowing the circuit element controlling section to control the operation of the circuit element so as to decrease the quantity of errors to be generated in the received signal due to the control of the operation of the circuit element by the circuit element controlling section, when it was decided in the correction possibility judging step that the error correcting section can not correct errors to be included in the received signal.

27. A digital receiver comprising a digital demodulating apparatus comprising:

a plurality of circuit elements constituting a tuner that performs channel select processing to a received signal that has been interleaved, and a demodulator that performs demodulation processing to the received signal from the tuner;

a deinterleaving section that performs deinterleave processing to the interleaved received signal from the tuner;

an error correcting section that corrects errors included in the received signal that has been deinterleaved by the deinterleaving section; and

a circuit element controlling section that controls an operation of at least one of the plurality of circuit elements,

the circuit element controlling section estimating the quantity of hypothetical errors to be generated in the received signal due to a control of an operation of a circuit element,

the circuit element controlling section judging from the estimated quantity of hypothetical errors whether or not the error correcting section can correct errors to be included in the received signal due to the control of the operation of the circuit element,

the circuit element controlling section controlling the operation of the circuit element so as to decrease the quantity of errors to be generated in the received signal due to the control of the operation of the circuit element, when the circuit element controlling section has decided that the error correcting section can not correct the errors to be included in the received signal,

the receiver performing reproduction processing to at least one of character data, image data, audio data, and program data, on the basis of the received signal demodulated by the digital demodulating apparatus.