Method and apparatus for integrated circuit fault isolation and failure analysis using linked tools cockpit

• US 20070118827A1
• Filed: 11/21/2005
• Published: 05/24/2007
• Est. Priority Date: 11/21/2005
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rahman, Asifur
• Application Number:
  US11/285,403
• Publication Number:
  US 20070118827A1
• Time in Patent Office: Days
• US Class Current: 716/102
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A microelectronic circuit debugging environment links development tools by correlating a selected element in a first tool with elements in the datasets of other tools. A signaling module instructs the other tools to display the correlated elements.

Claims

1. An apparatus comprising:

a database module to access a plurality of datasets of a plurality of development tools;

an event detector to detect when a user selects an element through a user interface of a first development tool;

correlation logic to map the selected element to a corresponding element of a second development tool; and

a signaling module to cause the second development tool to display the corresponding element.

2. The apparatus of claim 1, further comprising:

a display consolidator to redirect or duplicate a display from one of the plurality of development tools on a monitor.

3. The apparatus of claim 1, further comprising:

a utility module to launch the plurality of development tools automatically.

4. The apparatus of claim 1, further comprising:

a utility module to monitor the plurality of development tools and to restart a tool that terminates unexpectedly.

5. The apparatus of claim 1 wherein the plurality of development tools comprises at least two of a layout editor, a schematic editor, a circuit simulator, a logic simulator, a probing tool and a microscope.

6. A method comprising:

monitoring an operational state of a plurality of domain-specific tools;

detecting if an element of a first one of the tools is selected;

mapping the selected element to a corresponding element of a second one of the tools; and

signaling the second one of the tools to display the corresponding element.

7. The method of claim 6, further comprising:

mapping the selected element to a corresponding element of at least one additional domain-specific tool; and

signaling the at least one additional tool to cause the tool to display the corresponding element.

8. The method of claim 6 wherein the plurality of domain-specific tools comprise at least two of a schematic editor, a resistor-transistor-logic (“

RTL”

) simulator, a microelectronic circuit layout editor, an electrical signal probing tool, and a microscope.

9. A system comprising:

a plurality of applications to display data from at least three domains;

an input device to select an element displayed by a first one of the applications;

correlation logic to identify elements related to the selected element in a second one of the applications; and

a signaler to cause the second application to display the related elements.

10. The system of claim 9, further comprising at least one of:

an optical microscope and an electrical signal tester.

11. The system of claim 10 wherein the optical microscope is an infrared microscope.

12. A machine-readable medium containing instructions that, when executed by a processor, cause the processor to perform operations comprising:

detecting a predetermined user action;

identifying an element in a display of a first application that is affected by the user action;

correlating the element with a second element in a dataset of a second application; and

transmitting a message to cause the second application to select or highlight the second element.

13. The machine-readable medium of claim 12, wherein

transmitting the message is to cause a microscope to display an image of a selected portion of a microelectronic circuit.

14. The machine-readable medium of claim 12, wherein

transmitting the message is to cause a resistor-transistor logic (“

RTL”

) simulator to display a simulation of a selected signal.

15. The machine-readable medium of claim 12, wherein

transmitting the message is to cause a microelectronic circuit layout editor to display a design of a selected structure.

16. The machine-readable medium of claim 12, wherein

transmitting the message is to cause a schematic editor to display a selected portion of a circuit.