Generation of metal holes by via mutation
First Claim
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1. A method of producing a semiconductor interconnect architecture, the method comprising:
- providing a first metal layer;
providing a second metal layer;
providing a plurality of conductive vias interconnecting said first and second metal layers; and
said first-mentioned providing step including providing a plurality of holes in the first metal layer at respectively corresponding predetermined positions relative to respective ones of said plurality of vias.
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Abstract
A reduction in the intersection of vias on the last layer (“VL”) and holes in the last thin metal layer (“MLHOLE”) can be achieved without degrading product yield or robustness or increasing copper dishing. The mutation of some dense redundant VLs to MLHOLEs decreases the number of intersections between VLs and MLHOLEs.
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Citations
10 Claims
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1. A method of producing a semiconductor interconnect architecture, the method comprising:
- providing a first metal layer;
providing a second metal layer;
providing a plurality of conductive vias interconnecting said first and second metal layers; and
said first-mentioned providing step including providing a plurality of holes in the first metal layer at respectively corresponding predetermined positions relative to respective ones of said plurality of vias. - View Dependent Claims (2, 3, 4, 5)
- providing a first metal layer;
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6. A semiconductor interconnect architecture, the architecture comprising:
- a first metal layer;
a second metal layer;
a plurality of conductive vias interconnecting said first and second metal layers; and
said first metal layer having provided therein a plurality of holes at respectively corresponding predetermined positions relative to respective ones of said plurality of vias. - View Dependent Claims (7, 8, 9, 10)
- a first metal layer;
Specification