Switch circuit and method of switching radio frequency signals
First Claim
1. An RF switch circuit for switching RF signals, comprising:
- (a) a first input port receiving a first RF input signal;
(b) a second input port receiving a second RF input signal;
(c) an RF common port;
(d) a first switch transistor grouping comprising a plurality of FETs having channels series coupled in a stacked configuration, one end of the series-connected channels being a first node coupled to the first input port, the opposite end of the series-connected channels being a second node coupled to the RF common port, the first switch transistor grouping having a control node that is driven by a switch control signal (SW) and is coupled to a gate of each of the plurality of FETs of the grouping via a corresponding gate impedance;
(e) a second switch transistor grouping comprising a plurality of FETs having channels series coupled in a stacked configuration, one end of the series-connected channels being a first node coupled to the second input port, the opposite end of the series-connected channels being a second node coupled to the RF common port, the first switch transistor grouping having a control node that is driven by an inverse (SW_) of the switch control signal (SW) and is coupled to a gate of each of the plurality of FETs of the grouping via a corresponding gate impedance;
(f) a first shunt transistor grouping comprising one or more FETs arranged in a stacked configuration, one end of the series-connected channels being a first node coupled to the second input port, the opposite end of the series-connected channels being a second node coupled to ground, the first shunt transistor grouping having a control node that is driven by a switch control signal (SW) and is coupled to a gate of each of the one or more FETs of the grouping via a corresponding gate impedance; and
(g) a second shunt transistor grouping comprising one or more FETs arranged in a stacked configuration, one end of the series-connected channels being a first node coupled to the first input port, the opposite end of the series-connected channels being a second node coupled to ground, the first shunt transistor grouping having a control node that is driven by an inverse (SW_) of the switch control signal (SW) and is coupled to a gate of each of the one or more FETs of the grouping via a corresponding gate impedance;
(h) wherein the control signals SW and SW_have approximately equal magnitude but opposite polarity with respect to ground;
wherein, when SW is enabled, the first switch and shunt transistor groupings are enabled while the second switch and shunt transistor groupings are disabled, thereby passing the first RF input signal through to the RF common port and shunting the second RF input signal to ground; and
wherein when SW is disabled, the second switch and shunt transistor groupings are enabled while the first switch and shunt transistor groupings are disabled, thereby passing the second RF input signal through to the RF common port and shunting the first RF input signal to ground.
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Accused Products
Abstract
An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.
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Citations
5 Claims
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1. An RF switch circuit for switching RF signals, comprising:
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(a) a first input port receiving a first RF input signal;
(b) a second input port receiving a second RF input signal;
(c) an RF common port;
(d) a first switch transistor grouping comprising a plurality of FETs having channels series coupled in a stacked configuration, one end of the series-connected channels being a first node coupled to the first input port, the opposite end of the series-connected channels being a second node coupled to the RF common port, the first switch transistor grouping having a control node that is driven by a switch control signal (SW) and is coupled to a gate of each of the plurality of FETs of the grouping via a corresponding gate impedance;
(e) a second switch transistor grouping comprising a plurality of FETs having channels series coupled in a stacked configuration, one end of the series-connected channels being a first node coupled to the second input port, the opposite end of the series-connected channels being a second node coupled to the RF common port, the first switch transistor grouping having a control node that is driven by an inverse (SW_) of the switch control signal (SW) and is coupled to a gate of each of the plurality of FETs of the grouping via a corresponding gate impedance;
(f) a first shunt transistor grouping comprising one or more FETs arranged in a stacked configuration, one end of the series-connected channels being a first node coupled to the second input port, the opposite end of the series-connected channels being a second node coupled to ground, the first shunt transistor grouping having a control node that is driven by a switch control signal (SW) and is coupled to a gate of each of the one or more FETs of the grouping via a corresponding gate impedance; and
(g) a second shunt transistor grouping comprising one or more FETs arranged in a stacked configuration, one end of the series-connected channels being a first node coupled to the first input port, the opposite end of the series-connected channels being a second node coupled to ground, the first shunt transistor grouping having a control node that is driven by an inverse (SW_) of the switch control signal (SW) and is coupled to a gate of each of the one or more FETs of the grouping via a corresponding gate impedance;
(h) wherein the control signals SW and SW_have approximately equal magnitude but opposite polarity with respect to ground;
wherein, when SW is enabled, the first switch and shunt transistor groupings are enabled while the second switch and shunt transistor groupings are disabled, thereby passing the first RF input signal through to the RF common port and shunting the second RF input signal to ground; and
wherein when SW is disabled, the second switch and shunt transistor groupings are enabled while the first switch and shunt transistor groupings are disabled, thereby passing the second RF input signal through to the RF common port and shunting the first RF input signal to ground. - View Dependent Claims (2, 3, 4, 5)
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Specification