Transition areas for dense memory arrays

• US 20070120180A1
• Filed: 11/24/2006
• Published: 05/31/2007
• Est. Priority Date: 11/25/2005
• Status: Abandoned Application

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Irani, Rustom, Shappir, Assaf
• Application Number:
  US11/604,029
• Publication Number:
  US 20070120180A1
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F.

Claims

1. A non-volatile memory chip comprising:

word lines spaced a sub-F (sub-minimum feature size F) width apart; and

extensions of said word lines in at least two transition areas wherein neighboring said extensions in at least one of said transition areas are spaced at least F apart.

2. The chip according to claim 1 and wherein said transition areas are on different sides of an array of said word lines.

3. The chip according to claim 2 and wherein said array is a NROM (nitride read only memory) array.

4. The chip according to claim 1 and wherein said extensions are insulated from each other by a dielectric filler.

5. The chip according to claim 1 and wherein said extensions are connected to peripheral transistors.

6. The chip according to claim 4 and wherein said dielectric filler is at least one of oxide or oxynitride.

7. The chip according to claim 1 and wherein said word lines and said extensions are formed of at least one of the following conductive materials:

tungsten, salicide and silicide.

8. The chip according to claim 1 and wherein said word lines and said extensions are formed of polysilicon.

9. The chip according to claim 1 and wherein said extensions are integral to said word lines.

10. A non-volatile memory chip comprising:

a densely packed array with spacings between neighboring word lines of less than half the width of one of said word lines;

a loosely packed periphery; and

at least two transition areas connecting word lines of said densely packed array to said loosely packed periphery, wherein each said transition area connects only a portion of said word lines.

11. The chip according to claim 10 and wherein each said portion is every other word line.

12. The chip according to claim 11 and wherein extensions of said every other word lines are integral to said word lines.

13. The chip according to claim 10 and wherein said transition areas are on different sides of an array of said word lines.

14. The chip according to claim 13 and wherein said array is a NROM (nitride read only memory) array.

15. The chip according to claim 10 and wherein said extensions are insulated from each other by a dielectric filler.

16. The chip according to claim 15 and wherein said dielectric filler is at least one of oxide or oxynitride.

17. The chip according to claim 10 and wherein said word lines and said extensions are formed of at least one of the following conductive materials:

tungsten, salicide and silicide.

18. The chip according to claim 10 and wherein said word lines and said extensions are formed of polysilicon.

19. A method for word-line patterning of a non-volatile memory chip, the method comprising:

generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least a minimum feature size F.

20. The method according to claim 19 and wherein said generating comprises:

generating a first set of rows from said mask generated elements; and

generating a second set of rows, interleaved between said first set of rows, from said first set of rows.

21. The method according to claim 20 and wherein said first generating comprises:

creating rows of nitride hard mask where each row has a width of greater than 1F;

depositing word line material between said rows;

etching said word line material from a first transition area;

etching said rows from a second transition area; and

depositing oxide into said etched areas.

22. The method according to claim 21 and wherein said second generating comprises:

etching said nitride hard mask;

depositing nitride spacers in place of said rows of nitride; and

depositing word line material between said spacers.

23. The method according to claim 21 and wherein said second transition area is generally located on an opposite side of said word lines from said first transition area.

24. A non-volatile memory chip comprising:

word lines in a memory array with spacings between neighboring word lines of less than half the width of one of said word lines; and

extensions of said word lines in at least two transition areas wherein neighboring said extensions in at least one of said transition areas are spaced more than the width of one word line apart.

25. The chip according to claim 24 and wherein said transition areas are on different sides of an array of said word lines.

26. The chip according to claim 25 and wherein said array is a NROM (nitride read only memory) array.

27. The chip according to claim 24 and wherein said extensions are insulated from each other by a dielectric filler.

28. The chip according to claim 24 and wherein said extensions are connected to peripheral transistors.

29. The chip according to claim 27 and wherein said dielectric filler is at least one of oxide or oxynitride.

30. The chip according to claim 24 and wherein said word lines and said extensions are formed of at least one of the following conductive materials:

tungsten, salicide and silicide.

31. The chip according to claim 24 and wherein said word lines and said extensions are formed of polysilicon.

32. The chip according to claim 24 and wherein said extensions are integral to said word lines.